{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:30:44Z","timestamp":1761647444161},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540465591"},{"type":"electronic","value":"9783540465614"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11894063_24","type":"book-chapter","created":{"date-parts":[[2006,10,16]],"date-time":"2006-10-16T17:49:01Z","timestamp":1161020941000},"page":"298-310","source":"Crossref","is-referenced-by-count":54,"title":["Improving SHA-2 Hardware Implementations"],"prefix":"10.1007","author":[{"given":"Ricardo","family":"Chaves","sequence":"first","affiliation":[]},{"given":"Georgi","family":"Kuzmanov","sequence":"additional","affiliation":[]},{"given":"Leonel","family":"Sousa","sequence":"additional","affiliation":[]},{"given":"Stamatis","family":"Vassiliadis","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"24_CR1","first-page":"70","volume-title":"DATE","author":"L. Dadda","year":"2004","unstructured":"Dadda, L., Macchetti, M., Owen, J.: The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512). In: DATE, pp. 70\u201375. IEEE Computer Society, Los Alamitos (2004)"},{"key":"24_CR2","doi-asserted-by":"publisher","first-page":"222","DOI":"10.1109\/ARITH.2005.36","volume-title":"IEEE Symposium on Computer Arithmetic","author":"M. Macchetti","year":"2005","unstructured":"Macchetti, M., Dadda, L.: Quasi-pipelined hash circuits. In: IEEE Symposium on Computer Arithmetic, pp. 222\u2013229. IEEE Computer Society, Los Alamitos (2005)"},{"key":"24_CR3","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1145\/988952.989053","volume-title":"ACM Great Lakes Symposium on VLSI","author":"L. Dadda","year":"2004","unstructured":"Dadda, L., Macchetti, M., Owen, J.: An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512). In: Garrett, D., Lach, J., Zukowski, C.A. (eds.) ACM Great Lakes Symposium on VLSI, pp. 421\u2013425. ACM, New York (2004)"},{"key":"24_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"75","DOI":"10.1007\/3-540-45811-5_6","volume-title":"Information Security","author":"T. Grembowski","year":"2002","unstructured":"Grembowski, T., Lien, R., Gaj, K., Nguyen, N., Bellows, P., Flidr, J., Lehman, T., Schott, B.: Comparative analysis of the hardware implementations of hash functions SHA-1 and SHA-512. In: Chan, A.H., Gligor, V.D. (eds.) ISC 2002. LNCS, vol.\u00a02433, pp. 75\u201389. Springer, Heidelberg (2002)"},{"key":"24_CR5","doi-asserted-by":"crossref","unstructured":"McLoone, M., McCanny, J.V.: Efficient single-chip implementation of SHA-384 & SHA-512. In: proc. of IEEE International Conference on Field-Programmable Technology, pp. 311\u2013314 (2002)","DOI":"10.1109\/FPT.2002.1188699"},{"key":"24_CR6","doi-asserted-by":"publisher","first-page":"227","DOI":"10.1007\/s11227-005-0086-5","volume":"31","author":"N. Sklavos","year":"2005","unstructured":"Sklavos, N., Koufopavlou, O.: Implementation of the SHA-2 hash family standard using FPGAs. The Journal of Supercomputing\u00a031, 227\u2013248 (2005)","journal-title":"The Journal of Supercomputing"},{"key":"24_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"577","DOI":"10.1007\/3-540-46117-5_60","volume-title":"Field-Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream","author":"K.K. Ting","year":"2002","unstructured":"Ting, K.K., Yuen, S.C.L., Lee, K.-H., Leong, P.H.W.: An FPGA Based SHA-256 Processor. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol.\u00a02438, pp. 577\u2013585. Springer, Heidelberg (2002)"},{"key":"24_CR8","doi-asserted-by":"crossref","unstructured":"McEvoy, R.P., Crowe, F.M., Murphy, C.C., Marnane, W.P.: Optimisation of the SHA-2 family of hash functions on FPGAs. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI 2006), pp. 317\u2013322 (2006)","DOI":"10.1109\/ISVLSI.2006.70"},{"key":"24_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"591","DOI":"10.1007\/11556930_60","volume-title":"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation","author":"H.E. Michail","year":"2005","unstructured":"Michail, H.E., Kakarountas, A.P., Selimis, G.N., Goutis, C.E.: Optimizing SHA-1 hash function for high throughput with a partial unrolling study. In: Paliouras, V., Vounckx, J., Verkest, D. (eds.) PATMOS 2005. LNCS, vol.\u00a03728, pp. 591\u2013600. Springer, Heidelberg (2005)"},{"key":"24_CR10","unstructured":"NIST: Announcing the standard for secure hash standard, FIPS 180-1. Technical report, National Institute of Standards and Technology (1995)"},{"key":"24_CR11","unstructured":"NIST: The keyed-hash message authentication code (HMAC), FIPS 198. Technical report, National Institute of Standards and Technology (2002)"},{"key":"24_CR12","unstructured":"Omitted due to the blind review submission"},{"key":"24_CR13","doi-asserted-by":"crossref","unstructured":"Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G.K., Panainte, E.M.: The Molen polymorphic processor. IEEE Transactions on Computers, 1363\u20131375 (2004)","DOI":"10.1109\/TC.2004.104"},{"key":"24_CR14","unstructured":"Sklavos, N., Koufopavlou, O.: On the hardware implementation of the SHA-2 (256,384,512) hash functions. In: proc. of IEEE International symposium on Circuits and systems (ISCAS 2003), pp. 25\u201328 (2003)"},{"key":"24_CR15","unstructured":"HELION: Fast SHA-2 (256) hash core for xilinx FPGA (2005), http:\/\/www.heliontech.com\/"},{"key":"24_CR16","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"324","DOI":"10.1007\/978-3-540-24660-2_25","volume-title":"Topics in Cryptology \u2013 CT-RSA 2004","author":"R. Lien","year":"2004","unstructured":"Lien, R., Grembowski, T., Gaj, K.: A 1 Gbit\/s partially unrolled architecture of hash functions SHA-1 and SHA-512. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol.\u00a02964, pp. 324\u2013338. Springer, Heidelberg (2004)"}],"container-title":["Lecture Notes in Computer Science","Cryptographic Hardware and Embedded Systems - CHES 2006"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11894063_24.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,2]],"date-time":"2021-08-02T12:25:26Z","timestamp":1627907126000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11894063_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540465591","9783540465614"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/11894063_24","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}