{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T16:10:30Z","timestamp":1746115830325,"version":"3.40.4"},"publisher-location":"New York, NY","reference-count":86,"publisher":"Springer New York","isbn-type":[{"type":"print","value":"9781461448938"},{"type":"electronic","value":"9781461448945"}],"license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-1-4614-4894-5_7","type":"book-chapter","created":{"date-parts":[[2013,5,16]],"date-time":"2013-05-16T14:01:10Z","timestamp":1368712870000},"page":"181-195","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Related Work"],"prefix":"10.1007","author":[{"given":"Jo\u00e3o M. P.","family":"Cardoso","sequence":"first","affiliation":[]},{"given":"Jos\u00e9 Gabriel de","family":"F. Coutinho","sequence":"additional","affiliation":[]},{"given":"Pedro C.","family":"Diniz","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2013,5,17]]},"reference":[{"key":"7_CR1","doi-asserted-by":"crossref","unstructured":"J.M.P. Cardoso, P. Diniz, Compilation Techniques for Reconfigurable Architectures (Springer, New York, 2008)","DOI":"10.1007\/978-0-387-09671-1"},{"issue":"4","key":"7_CR2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1749603.1749604","volume":"42","author":"J.M.P. Cardoso","year":"2010","unstructured":"J.M.P. Cardoso, P. Diniz, M. Weinhardt, Compiling for reconfigurable computing: a survey. ACM. Comput. Surv. (CSUR), 42(4), 1\u201365 (2010) June, Article 13","journal-title":"ACM. Comput. Surv. (CSUR)"},{"issue":"2\u20133","key":"7_CR3","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1016\/j.micpro.2004.06.007","volume":"29","author":"P. Diniz","year":"2005","unstructured":"P. Diniz, M. Hall, J. Park, B. So, H. Ziegler, Automatic mapping of c to FPGAs with the defacto compilation and synthesis systems. J. Microprocess. Microsyst. 29(2\u20133), 51\u201362 (2005) 1 April","journal-title":"J. Microprocess. Microsyst."},{"issue":"2","key":"7_CR4","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1109\/MDT.2003.1188264","volume":"20","author":"JMP Cardoso","year":"2003","unstructured":"J.M.P. Cardoso, H. Neto, Compilation for FPGA-based reconfigurable hardware. IEEE. Des. Test. Comput Mag. 20(2), 65\u201375 (2003) March\/April","journal-title":"IEEE. Des. Test. Comput Mag."},{"issue":"2","key":"7_CR5","doi-asserted-by":"crossref","first-page":"234","DOI":"10.1109\/43.908452","volume":"20","author":"M. Weinhardt","year":"2001","unstructured":"M. Weinhardt, W. Luk, Pipeline vectorization. IEEE. Trans. CAD. Integr. Circuits. Syst. 20(2), 234\u2013248 (2001)","journal-title":"IEEE. Trans. CAD. Integr. Circuits. Syst."},{"issue":"3","key":"7_CR6","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1109\/TCAD.2009.2013541","volume":"28","author":"Q Liu","year":"2009","unstructured":"Q. Liu, G. Constantinides, K. Masselos, P. Cheung, Combining data reuse with data-level parallelization for fpga targeted hardware compilation: a geometric programming framework. IEEE. Trans. Comput. Aided. Des. 28(3), 305\u2013315 (2009)","journal-title":"IEEE. Trans. Comput. Aided. Des."},{"issue":"12","key":"7_CR7","doi-asserted-by":"publisher","first-page":"1520","DOI":"10.1109\/TC.2005.201","volume":"54","author":"D Lee","year":"2005","unstructured":"D. Lee, A. Abdul Gaffar, O. Mencer, W. Luk, Optimizing hardware function evaluation. IEEE. Trans. Comput. 54(12), 1520\u20131531 (2005)","journal-title":"IEEE. Trans. Comput."},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Y. Yankova, K. Bertels, S. Vassiliadis, R. Meeuws, A. Virginia, Automated HDL Generation: Comparative Evaluation, in Proc. Int. Symp. on Circuits and Systems (ISCAS2007), May 2007","DOI":"10.1109\/ISCAS.2007.378622"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"E. Panainte, K. Bertels, S. Vassiliadis, The Molen compiler for reconfigurable processors. ACM. Trans. Embed. Comput. Syst. (TECS) 6(1) (2007) Article 6, Feb","DOI":"10.1145\/1210268.1210274"},{"issue":"2","key":"7_CR10","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1007\/s11265-006-7268-0","volume":"43","author":"E Panainte","year":"2006","unstructured":"E. Panainte, K. Bertels, S. Vassiliadis, Interprocedural compiler optimization for partial run-time reconfiguration. J. VLSI Sig. Proc. 43(2), 161\u2013172 (2006)","journal-title":"J. VLSI Sig. Proc."},{"issue":"10","key":"7_CR11","doi-asserted-by":"publisher","first-page":"1362","DOI":"10.1109\/TC.2003.1234532","volume":"52","author":"J Cardoso","year":"2003","unstructured":"J. Cardoso, On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures. IEEE. Trans. Comput. 52(10), 1362\u20131375 (2003)","journal-title":"IEEE. Trans. Comput."},{"key":"7_CR12","unstructured":"Q. Liu, T. Todman, J. Coutinho, W. Luk, G. Constantinides, Optimising designs by combining model-based and pattern-based transformations, in Proceedings of the 19th International Conference on Field Programmable Logic and Applications (FPL\u201909), Aug. 31\u2013Sept. 2, pp. 308\u2013313 (2009)"},{"key":"7_CR13","doi-asserted-by":"crossref","unstructured":"J. Coutinho, J. Jiang, W. Luk, Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation, in Proceedings of IEEE Symposium on Field Programmable Custom Computing Machines (FCCM\u201905), 18\u201320 April, pp. 245\u2013254 (2005)","DOI":"10.1109\/FCCM.2005.44"},{"issue":"5","key":"7_CR14","doi-asserted-by":"publisher","first-page":"88","DOI":"10.1109\/MM.2010.91","volume":"30","author":"K Bertels","year":"2010","unstructured":"K. Bertels, V. Sima, Y. Yankova, G. Kuzmanov, W. Luk, J. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto, A. Michelotti, HArtes: hardware-software codesign for heterogeneous multicore platforms. IEEE. Micro. 30(5), 88\u201397 (2010)","journal-title":"IEEE. Micro."},{"key":"7_CR15","doi-asserted-by":"crossref","unstructured":"K.L.M. Bertels, Hardware\/Software Co-design for Heterogeneous Multi-core Platforms (Springer, Drodrecht Heidelberg London New York, 2012)","DOI":"10.1007\/978-94-007-1406-9"},{"key":"7_CR16","doi-asserted-by":"crossref","unstructured":"G. Kuzmanov, V. Sima, K. Bertels, G. Coutinho, W. Luk, G. Marchiori, R. Tripiccione, F. Ferrandi, hArtes: holistic approach to reconfigurable real-time embedded systems, in Reconfigurable Computing\u2014From FPGAs to Hardware\/Software Codesign (Springer, New York, 2011)","DOI":"10.1007\/978-1-4614-0061-5_5"},{"issue":"11","key":"7_CR17","doi-asserted-by":"publisher","first-page":"1363","DOI":"10.1109\/TC.2004.104","volume":"53","author":"S Vassiliadis","year":"2004","unstructured":"S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, E. Panainte, The molen polymorphic processor. IEEE. Trans. Comput. 53(11), 1363\u20131375 (2004)","journal-title":"IEEE. Trans. Comput."},{"key":"7_CR18","doi-asserted-by":"crossref","unstructured":"C. Morra, J.M.P. Cardoso, J. Becker, Using rewriting-logic to match patterns of instructions from a compiler intermediate form to coarse-grained processing elements, in Proc. of 21st IEEE Int. Parallel & Distributed Processing Symp. (IPDPS\u201907), Long Beach, USA, 2007","DOI":"10.1109\/IPDPS.2007.370369"},{"key":"7_CR19","doi-asserted-by":"crossref","unstructured":"C. Morra, Configware design space exploration using rewriting-logic, in Proceedings of the 16th Int. Conf. on Field Programmable Logic and Applications (FPL\u201906), Madrid, Spain, 2006","DOI":"10.1109\/FPL.2006.311348"},{"key":"7_CR20","doi-asserted-by":"crossref","unstructured":"C. Morra, M. Sackmann, S. Shukla, J. Becker, R. Hartenstein, From equation to VHDL: using rewriting-logic for automated function generation, in Proc. of the 16th Int. Conf. on Field Programmable Logic and Applications (FPL\u201906), Madrid, Spain, 2006","DOI":"10.1109\/FPL.2006.311289"},{"key":"7_CR21","unstructured":"C. Morra, M. Sackmann, J. Becker, R. Hartenstein, Using rewriting logic to generate different implementations of polynomial approximations in coarse-grained architectures, in Proc. of the 2nd Int. Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC\u201906), July 2006"},{"key":"7_CR22","unstructured":"O. Mencer, D.J. Pearce, L.W. Howes, W. Luk, Design space exploration with a stream compiler, in Proc. of the Int. Conf. on Field Programmable Technology (FPT\u201903), IEEE (2003)"},{"key":"7_CR23","doi-asserted-by":"crossref","unstructured":"Y. Yankova, K.L.M. Bertels, S. Vassiliadis, R. J. Meeuws, A.J.R. Virginia, Automated HDL generation: comparative evaluation, in Proc. of the Int. Symp. on Circuits and Systems (ISCAS2007), May 2007","DOI":"10.1109\/ISCAS.2007.378622"},{"key":"7_CR24","unstructured":"P. Diniz, J. Park, Automatic synthesis of data storage and control structures for FPGA-based computing machines, in Proc. of the IEEE Symp. on FPGAs for Custom Computing Machines, Oct. (2000) pp. 91\u2013100"},{"key":"7_CR25","doi-asserted-by":"crossref","unstructured":"N. Baradaran, P. Diniz, Memory parallelism using custom array mapping to heterogeneous storage structures, in Proc. of the 2006 IEEE Int. Conf. on Field-Programmable Logic (FPL\u201906), August (2006)","DOI":"10.1109\/FPL.2006.311241"},{"key":"7_CR26","doi-asserted-by":"crossref","unstructured":"J.M.P. Cardoso, M. Weinhardt, Compilation and temporal partitioning for a coarse-grain reconfigurable architecture (Chap. 9), in New Algorithms, Architectures, and Applications for Reconfigurable Computing (Springer, US, 2005), pp. 105\u2013115","DOI":"10.1007\/1-4020-3128-9_9"},{"key":"7_CR27","doi-asserted-by":"crossref","unstructured":"J.M.P. Cardoso, Dynamic loop pipelining in data-driven architectures, in Proc. of the ACM Int. Conf. on Computing Frontiers (CF\u201905), Ischia, Italy, ACM Press, 4\u20136 May 2005, pp. 106\u2013115","DOI":"10.1145\/1062261.1062283"},{"issue":"3","key":"7_CR28","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1529255.1529261","volume":"14","author":"J. Clarke","year":"2009","unstructured":"J. Clarke, G.A. Constantinides, P.Y.K. Cheung, Word-length selection for power minimization via non-linear optimization. ACM. Trans. Des. Autom. Electron. Syst. 14(3), 1\u201328 (2009)","journal-title":"ACM. Trans. Des. Autom. Electron. Syst."},{"issue":"1","key":"7_CR29","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1145\/1124713.1124716","volume":"11","author":"G Constantinides","year":"2006","unstructured":"G. Constantinides, Word-length optimization for differentiable nonlinear systems. ACM. Trans. Des. Autom. Electron. Syst. 11(1), 26\u201343 (2006)","journal-title":"ACM. Trans. Des. Autom. Electron. Syst."},{"key":"7_CR30","unstructured":"Altera Corporation, Nios II C2H compiler user guide (Nov. 2009)"},{"key":"7_CR31","unstructured":"Catapult C Synthesis Overview, http:\/\/www.mentor.com\/esl\/catapult\/ (Dec. 2010)"},{"key":"7_CR32","unstructured":"T. Bollaert, Catapult synthesis: a practical introduction to interactive C synthesis (Chap. 3), in High-Level Synthesis: From Algorithm to Digital Circuit, ed. by P. Coussy, A. Morawiec (Springer, Berlin, 2008)"},{"key":"7_CR33","unstructured":"Xilinx Inc., Vivado Design Suite, User Guide, High-Level Synthesis, UG902 (v2012.2), July, 25, 2012"},{"key":"7_CR34","doi-asserted-by":"crossref","unstructured":"Y. Yankova, G. Kuzmanov, K. Bertels, G. Gaydadjiev, Y. Lu, S. Vassiliadis, DWARV: delftworkbench automated reconfigurable VHDL generator, in Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL\u201907), Amsterdam, The Netherlands, 27\u201329 Aug. 2007, pp. 697\u2013701","DOI":"10.1109\/FPL.2007.4380748"},{"key":"7_CR35","doi-asserted-by":"crossref","unstructured":"R. Nane, V.M. Sima, B. Olivier, R. Meeuws, Y. Yankova, K.L.M. Bertels, \u201cDWARV 2.0: a CoSy-based C-to-VHDL hardware compiler, in Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL\u20192012), Oslo, Norway, August 2012","DOI":"10.1109\/FPL.2012.6339221"},{"key":"7_CR36","unstructured":"Nallatech, http:\/\/www.nallatech.com. Accessed Dec 2010"},{"issue":"3","key":"7_CR37","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/MC.2007.107","volume":"40","author":"J Tripp","year":"2007","unstructured":"J. Tripp, M. Gokhale, K. Peterson, Trident: from high-level language to hardware circuitry. IEEE. Comp. 40(3), 28\u201337 (2007)","journal-title":"IEEE. Comp."},{"key":"7_CR38","doi-asserted-by":"crossref","unstructured":"G. Villarreal, A. Park, W. Najjar, R. Halstead, Designing modular hardware accelerators in c with ROCCC 2.0, in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM\u201910), IEEE Computer Society, Washington, DC, USA, April 2010, pp. 127\u2013134","DOI":"10.1109\/FCCM.2010.28"},{"key":"7_CR39","doi-asserted-by":"crossref","unstructured":"Z. Guo, W. Najjar, A. Buyukkurt, Efficient hardware code generation for FPGAs. ACM. Trans. Archit. Compil. Optim. 5(1) (2008) Article 6","DOI":"10.1145\/1369396.1369402"},{"key":"7_CR40","unstructured":"S. Gupta, R. Gupta, N. Dutt, A. Nicolau, SPARK: A Parallelizing Approach to the High-level Synthesis of Digital Circuits, 1st edn. (Springer, May 2004). Project page: http:\/\/mesl.ucsd.edu\/spark"},{"key":"7_CR41","unstructured":"M. Bowen, Handel-C Language Ref. Manual, 2.1 edn. Embedded Solutions Ltd., (1998)"},{"key":"7_CR42","unstructured":"Mentor Graphics, Handel-C Language Reference Manual (2012)"},{"key":"7_CR43","unstructured":"Mitrionics AB Inc., The Mitrion Processor, Product Overview (Sweden, 2005). http:\/\/www.mitrion.com. Accessed Dec 2010"},{"key":"7_CR44","unstructured":"Mitrionics, The Mitrion Accelerated Computing Platform (2012), http:\/\/www.mitrionics.com\/"},{"key":"7_CR45","doi-asserted-by":"publisher","first-page":"63","DOI":"10.1109\/MC.2003.1220583","volume":"8","author":"W Najjar","year":"2003","unstructured":"W. Najjar, W. Bohm, B. Draper, J. Hammes, R. Rinker, J. Beveridge, M. Chawathe, C. Ross, High-level abstraction for reconfigurable computing. IEEE. Comput. 8, 63\u201369 (2003)","journal-title":"IEEE. Comput."},{"key":"7_CR46","unstructured":"M. Gokhale, J. Stone, J. Arnold, M. Kalinowski, Stream-oriented FPGA computing in the streams-c high level language, in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM\u201900), April 2000, pp. 126\u2013135"},{"key":"7_CR47","volume-title":"A malleable architecture generator for FPGA computing","author":"M Gokhale","year":"1996","unstructured":"M. Gokhale, J. Kaba, A. Marks, J. Kim, A malleable architecture generator for FPGA computing (SPIE 96, USA, 1996)"},{"key":"7_CR48","unstructured":"Impulse Accelerated Technologies, Inc., http:\/\/www.impulseaccelerated.com\/ (Dec 2010)"},{"key":"7_CR49","unstructured":"D. Pellerin, S. Thibault, Practical FPGA programming in C (Prentice Hall Professional Technical Reference, 2005)"},{"key":"7_CR50","unstructured":"1666\u20132011\u2014IEEE Standard for Standard SystemC Language, Reference Manual, Institute of Electrical and Electronics Engineers, Inc., http:\/\/www.systemc.org"},{"key":"7_CR51","unstructured":"Maxeler Tech., Maxcompiler White Paper, http:\/\/maxeler.com (2011)"},{"key":"7_CR52","doi-asserted-by":"crossref","unstructured":"C. Huang, S. Ravi, A. Raghunathan, N. Jha, Synthesis of heterogeneous distributed architectures for memory-intensive applications, in Proceedings International Conference on Computer-Aided Design (ICCAD\u201903), Nov. 2003, pp. 46\u201353","DOI":"10.1109\/ICCAD.2003.159669"},{"key":"7_CR53","unstructured":"Automatically Tuned Linear Algebra Software (ATLAS), http:\/\/math-atlas.sourceforge.net\/"},{"key":"7_CR54","doi-asserted-by":"crossref","unstructured":"A. Tiwari, C. Chen, J, Chame, M. Hall, J. Hollingsworth, A scalable auto-tuning framework for compiler optimizations, in Proceedings of the International Symposium on Parallel and Distributed Processing (IPDPS\u201909), IEEE Computer Society, Washington, DC, USA, 2009, pp. 1\u201312","DOI":"10.1109\/IPDPS.2009.5161054"},{"key":"7_CR55","doi-asserted-by":"crossref","unstructured":"J. Xiong, J. Johnson, R. Johnson, D. Padua, SPL: a language and compiler for DSP algorithms, in Proceedings of the ACM Conference on Programming Language Design and Implementation (PLDI\u201901), ACM, New York, NY, USA, June 2001, pp. 298\u2013308","DOI":"10.1145\/381694.378860"},{"key":"7_CR56","doi-asserted-by":"crossref","unstructured":"C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, R. Zafalon, S. Bocchio, M. Wouters, G. Vanmeerbeeck, P. Avasare, C. Couvreur, L. Onesti, C. Kavka, A. Turco, U. Bondi, G. Mariani, E. Villar, H. Posadas, C. Y. q. Wu, F. Dongrui, Z. Hao, T. Shibin, Multicube: multi-objective design space exploration of multi-core architectures, in Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI\u201910), Kefalonia, Greece, July 5\u20137, 2010, pp. 488-493. Project webpage: http:\/\/www.multicube.eu\/","DOI":"10.1109\/ISVLSI.2010.67"},{"key":"7_CR57","doi-asserted-by":"crossref","unstructured":"M. Christen, O. Schenk, H. Burkhart, Patus: a code generation and autotuning framework for parallel iterative stencil computations on modern microarchitectures, in Proceedings of the IEEE International Parallel & Distributed Processing Symposium (IPDPS\u201911) (IEEE Computer Society, 2011), pp. 676\u2013687","DOI":"10.1109\/IPDPS.2011.70"},{"key":"7_CR58","unstructured":"CETUS\u2014A Source-To-Source Compiler Infrastructure For C Programs, http:\/\/cetus.ecn.purdue.edu\/"},{"key":"7_CR59","doi-asserted-by":"crossref","unstructured":"C. Bastoul, Code generation in the polyhedral model is easier than you think, in Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT \u201804) (IEEE Computer Society, Washington), pp. 7\u201316","DOI":"10.1109\/PACT.2004.1342537"},{"key":"7_CR60","doi-asserted-by":"crossref","unstructured":"M. Hall, J. Chame, C. Chen, J. Shin, G. Rudy, M. Khan, Loop transformation recipes for code generation and auto-tuning, in Proceedings of the 22nd International Conference on Languages and Compilers for Parallel Computing (LCPC\u201909) (Newark, DE, Springer-Verlag, Berlin, Heidelberg, 2010) pp. 50\u201364","DOI":"10.1007\/978-3-642-13374-9_4"},{"issue":"6","key":"7_CR61","doi-asserted-by":"crossref","first-page":"675","DOI":"10.1002\/spe.1089","volume":"42","author":"Q. Yi","year":"2012","unstructured":"Q. Yi, Poet: a scripting language for applying parameterized source-to-source program transformations. Softw. Pract. Exp. 42(6), 675\u2013706 (2012)","journal-title":"Softw. Pract. Exp."},{"key":"7_CR62","doi-asserted-by":"crossref","unstructured":"G. Kiczales, Aspect-oriented programming. ACM. Comput. Surv. 28(4) (1996)","DOI":"10.1145\/242224.242420"},{"key":"7_CR63","doi-asserted-by":"crossref","unstructured":"G. Kiczales, J. Lamping, A. Mendhekar, C. Maeda, C. Videira Lopes, J.-Marc Loingtier, J. Irwin, Aspect oriented programming, in Proceedings of the European Conference on Object-Oriented Programming (ECOOP\u201997) (LNCS 1241 Springer-Verlag, Finland, June 1997), pp. 220\u2013242","DOI":"10.1007\/BFb0053381"},{"key":"7_CR64","unstructured":"J. Gradecki, N. Lesiecki, Mastering AspectJ: Aspect-Oriented Programming in Java (Wiley, New York, 2003)"},{"key":"7_CR65","unstructured":"D. Lohmann, O. Spinczyk, Aspect-Oriented Programming with C++ and AspectC++. Tutorial, AOSD\u20192007, March 13, 2007"},{"key":"7_CR66","unstructured":"O. Spinczyk, A. Gal, W. Schr\u00f6der-Preikschat, AspectC++: an aspect-oriented extension to the C++ programming language, in Proceedings of the 40th International Conference on Tools Pacific: Objects for Internet, Mobile and Embedded Applications, pp. 53\u201360 (2002)"},{"key":"7_CR67","doi-asserted-by":"crossref","unstructured":"B. Harbulot, J.R. Gurd, A join point for loops in AspectJ, in Proceedings of the 5th International Conference on Aspect-Oriented Software Development (AOSD \u201906) (ACM, NY, USA, 2006), pp. 63\u201374","DOI":"10.1145\/1119655.1119666"},{"key":"7_CR68","unstructured":"M. Poggi. @AspectJ\u2014An extension to the AspectJ join point selection mechanism to support @Java annotation meta-facility. Master thesis (in Italian), Universit\u00e0 di Genova, Oct 2009"},{"key":"7_CR69","doi-asserted-by":"crossref","unstructured":"M. Eichberg, M. Mezini, K. Ostermann, Pointcuts as functional queries, in Programming Languages and Systems, ed. by W.-N. Chin (Springer, Berlin\/Heidelberg, 2004), pp. 366\u2013381","DOI":"10.1007\/978-3-540-30477-7_25"},{"key":"7_CR70","doi-asserted-by":"crossref","unstructured":"W. Luk, J. Coutinho, T. Todman, Y. Lam, W. Osborne, K. Susanto, Q. Liu, W. Wong, A high-level compilation toolchain for heterogeneous systems, in Proceedings of the IEEE International SOC Conference (SOCC\u201909), Sept. 2009, pp. 9\u201318","DOI":"10.1109\/SOCCON.2009.5398108"},{"key":"7_CR71","doi-asserted-by":"crossref","unstructured":"A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier, M. Wrighton, Design patterns for reconfigurable computing, in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM\u201904), April 20\u201323, 2004, pp. 13\u201323","DOI":"10.1109\/FCCM.2004.29"},{"key":"7_CR72","doi-asserted-by":"crossref","unstructured":"M. Boden, T. Fiebig, T. Meissner, S. Ruelke, J. Becker, High-level synthesis of hw tasks targeting run-time reconfigurable FPGAs, in Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS), Reconfigurable Architectures Workshop (RAW), Long Beach, CA, USA, Mar 2007","DOI":"10.1109\/IPDPS.2007.370390"},{"key":"7_CR73","doi-asserted-by":"crossref","unstructured":"A. Brito, M. Kuehnle, E. Melcher, J. Becker, A general purpose partially reconfigurable processor simulator (PReProS), in Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS\u201907), Reconfigurable Architectures Workshop (RAW), Long Beach, CA, USA, Mar 2007","DOI":"10.1109\/IPDPS.2007.370375"},{"key":"7_CR74","volume-title":"Strategies to On- Line Failure Recovery in Self-Adaptive Systems based on Dynamic and Partial Reconfiguration","author":"K Paulsson","year":"2006","unstructured":"K. Paulsson, M. H\u00fcbner, J. Becker, Strategies to On- Line Failure Recovery in Self-Adaptive Systems based on Dynamic and Partial Reconfiguration (AHS2006, Turkey, 2006)"},{"key":"7_CR75","doi-asserted-by":"crossref","unstructured":"K. Paulsson, M. H\u00fcbner, J. Becker: On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives, SBCCI2006, Brazil","DOI":"10.1145\/1150343.1150389"},{"key":"7_CR76","unstructured":"A. Thomas, J. Becker, Multi-grained reconfigurable hardware architecture with online-adaptive routing techniques, in IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005), Perth, Australia, Oct. 17\u201319, 2005"},{"key":"7_CR77","unstructured":"M. H\u00fcbner, C. Schuck, M. K\u00fchnle, J. Becker, New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits, in Proceedings of the 2006 IEEE Annual Symposium on VLSI (ISVLSI), Karlsruhe, Germany, March 2006"},{"key":"7_CR78","doi-asserted-by":"crossref","unstructured":"C. Schuck, M. Kuehnle, M. Huebner, J. Becker, A framework for dynamic 2D placement on FPGAs, in Proceedings of the IEEE International Symposium on Parallel and Distributed Processing (IPDPS\u20192008), IEEE Computer Society, 2008, pp. 1\u20137","DOI":"10.1109\/IPDPS.2008.4536512"},{"key":"7_CR79","doi-asserted-by":"crossref","unstructured":"P. Sedcole, P. Cheung, G. Constantinides, W. Luk, On-chip communication in run-time assembled reconfigurable systems, in Proceedings International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July 2006, pp. 168\u2013176","DOI":"10.1109\/ICSAMOS.2006.300824"},{"key":"7_CR80","doi-asserted-by":"crossref","unstructured":"M. Huebner, L. Braun, D. Goehringer, J. Becker, Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems, in Proceedings of the IEEE International Symposium on Parallel and Distributed Processing (IPDPS\u20192008), IEEE Computer Society, 2008, pp. 1\u20136","DOI":"10.1109\/IPDPS.2008.4536504"},{"key":"7_CR81","doi-asserted-by":"crossref","unstructured":"M. Kuehnle, M. Huebner, J. Becker, A. Deledda, C. Mucci, F. Ries, A.M. Coppola, L. Pieralisi, R. Locatelli, G. Maruccia, T. DeMarco, F. Campi, An interconnect strategy for a heterogeneous, reconfigurable SoC. Des. Test. Comput. IEEE. 25(5), 442\u2013451","DOI":"10.1109\/MDT.2008.150"},{"key":"7_CR82","unstructured":"Xilinx Inc., XST User Guide, UG627 (v 11.3), September 16, 2009"},{"key":"7_CR83","unstructured":"Xilinx Inc., XPower Estimator User Guide, UG440 (v2012.2\/14.2), July, 25, 2012"},{"key":"7_CR84","unstructured":"Xilinx Inc., Command Line Tools User Guide, UG628 (v 14.2), July, 25, 2012"},{"key":"7_CR85","doi-asserted-by":"crossref","unstructured":"N. Voros, A. Rosti, M. H\u00fcbner, Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach (Springer-Verlag, 2009)","DOI":"10.1007\/978-90-481-2427-5"},{"key":"7_CR86","doi-asserted-by":"crossref","unstructured":"A. Grasset, P. Brelet, P. Millet, P. Bonnot, F. Campi, N. Voros, M. Huebner, M. Kuehnle, F. Thoma, W. Putzke-Roeming, A. Schneider, Morpheus: exploitation of reconfiguration for increased run-time flexibility and self-adaptive capabilities in future SoCs, in Reconfigurable Computing: From FPGAs to Hardware\/Software Codesign (Springer, New York, 2011)","DOI":"10.1007\/978-1-4614-0061-5_4"}],"container-title":["Compilation and Synthesis for Embedded Reconfigurable Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4614-4894-5_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T10:23:15Z","timestamp":1746008595000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-1-4614-4894-5_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9781461448938","9781461448945"],"references-count":86,"URL":"https:\/\/doi.org\/10.1007\/978-1-4614-4894-5_7","relation":{},"subject":[],"published":{"date-parts":[[2013]]},"assertion":[{"value":"17 May 2013","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}