{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:44:14Z","timestamp":1761648254679,"version":"3.40.3"},"publisher-location":"Cham","reference-count":19,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319162133"},{"type":"electronic","value":"9783319162140"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-16214-0_19","type":"book-chapter","created":{"date-parts":[[2015,3,30]],"date-time":"2015-03-30T22:56:39Z","timestamp":1427756199000},"page":"229-240","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Dual CLEFIA\/AES Cipher Core on FPGA"],"prefix":"10.1007","author":[{"given":"Jo\u00e3o Carlos","family":"Resende","sequence":"first","affiliation":[]},{"given":"Ricardo","family":"Chaves","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,3,31]]},"reference":[{"key":"19_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1007\/978-3-540-68164-9_2","volume-title":"Progress in Cryptology \u2013 AFRICACRYPT 2008","author":"P Bulens","year":"2008","unstructured":"Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on virtex-5 FPGAs. In: Vaudenay, S. (ed.) AFRICACRYPT 2008. LNCS, vol. 5023, pp. 16\u201326. Springer, Heidelberg (2008)"},{"key":"19_CR2","doi-asserted-by":"crossref","unstructured":"Chaves, R., Kuzmanov, G., Vassiliadis, S., Sousa, L.: Reconfigurable memory based AES co-processor. In: 20th International on Parallel and Distributed Processing Symposium, IPDPS 2006, p. 8. IEEE (2006)","DOI":"10.1109\/IPDPS.2006.1639441"},{"key":"19_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"319","DOI":"10.1007\/978-3-540-45238-6_26","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2003","author":"P Chodowiec","year":"2003","unstructured":"Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the AES algorithm. In: Walter, C.D., Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 319\u2013333. Springer, Heidelberg (2003)"},{"issue":"1","key":"19_CR4","first-page":"3","volume":"3","author":"S Drimer","year":"2010","unstructured":"Drimer, S., G\u00fcneysu, T., Paar, C.: DSPs, BRAMs, and a pinch of logic: Extended recipes for AES on FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3(1), 3 (2010)","journal-title":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)"},{"key":"19_CR5","doi-asserted-by":"crossref","unstructured":"El Maraghy, M., Hesham, S., Abd El Ghany, M.A.: Real-time efficient FPGA implementation of aes algorithm. In: 2013 IEEE 26th International on SOC Conference (SOCC), pp. 203\u2013208. IEEE (2013)","DOI":"10.1109\/SOCC.2013.6749688"},{"issue":"5","key":"19_CR6","doi-asserted-by":"publisher","first-page":"468","DOI":"10.1109\/TPDS.2005.51","volume":"16","author":"AJ Elbirt","year":"2005","unstructured":"Elbirt, A.J., Paar, C.: An instruction-level distributed processor for symmetric-key cryptography. IEEE Transactions on Parallel and Distributed Systems 16(5), 468\u2013480 (2005)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"19_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"427","DOI":"10.1007\/11545262_31","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"T Good","year":"2005","unstructured":"Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 427\u2013440. Springer, Heidelberg (2005)"},{"key":"19_CR8","unstructured":"HELION. http:\/\/www.heliontech.com"},{"key":"19_CR9","doi-asserted-by":"crossref","unstructured":"Kashyap, H., Chaves, R.: Secure partial dynamic reconfiguration with unsecured external memory. In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1\u20137. IEEE (2014)","DOI":"10.1109\/FPL.2014.6927477"},{"key":"19_CR10","doi-asserted-by":"crossref","unstructured":"Kryjak, T., Gorgon, M.: Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA. In: International Conference on Field Programmable Logic and Applications, FPL 2009, pp. 373\u2013378. IEEE (2009)","DOI":"10.1109\/FPL.2009.5272264"},{"key":"19_CR11","doi-asserted-by":"crossref","unstructured":"Liu, Q., Xu, Z., Yuan, Y.: A 66.1 Gbps single-pipeline AES on FPGA. In: 2013 International Conference on Field-Programmable Technology (FPT), pp. 378\u2013381. IEEE (2013)","DOI":"10.1109\/FPT.2013.6718392"},{"key":"19_CR12","unstructured":"NIST: FIPS 197: Advanced encryption standard (AES). Federal Information Processing Standards Publication 197, 441\u20130311 (2001)"},{"key":"19_CR13","doi-asserted-by":"crossref","unstructured":"Proenca, P., Chaves, R.: Compact CLEFIA implementation on FPGAs. In: 2011 International Conference on Field Programmable Logic and Applications (FPL), pp. 512\u2013517. IEEE (2011)","DOI":"10.1109\/FPL.2011.101"},{"key":"19_CR14","doi-asserted-by":"crossref","unstructured":"Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.: Compact and efficient encryption\/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: Proceedings of the International Conference on Information Technology: Coding and Computing, ITCC 2004, vol. 2, pp. 583\u2013587. IEEE (2004)","DOI":"10.1109\/ITCC.2004.1286716"},{"key":"19_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1007\/978-3-540-74619-5_12","volume-title":"Fast Software Encryption","author":"T Shirai","year":"2007","unstructured":"Shirai, T., Shibutani, K., Akishita, T., Moriai, S., Iwata, T.: The 128-Bit blockcipher CLEFIA (Extended Abstract). In: Biryukov, A. (ed.) FSE 2007. LNCS, vol. 4593, pp. 181\u2013195. Springer, Heidelberg (2007)"},{"key":"19_CR16","doi-asserted-by":"crossref","unstructured":"Singh, H., Lee, M.H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Chaves Filho, E.M.: MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers 49(5), 465\u2013481 (2000)","DOI":"10.1109\/12.859540"},{"issue":"12","key":"19_CR17","doi-asserted-by":"publisher","first-page":"1454","DOI":"10.1109\/TC.2002.1146712","volume":"51","author":"N Sklavos","year":"2002","unstructured":"Sklavos, N., Koufopavlou, O.: Architectures and VLSI implementations of the AES-proposal Rijndael. IEEE Transactions on Computers 51(12), 1454\u20131459 (2002)","journal-title":"IEEE Transactions on Computers"},{"key":"19_CR18","doi-asserted-by":"crossref","unstructured":"Tsunoo, Y., Tsujihara, E., Shigeri, M., Suzaki, T., Kawabata, T.: Cryptanalysis of CLEFIA using multiple impossible differentials. In: International Symposium on Information Theory and its Applications, ISITA 2008, pp. 1\u20136. IEEE (2008)","DOI":"10.1109\/ISITA.2008.4895639"},{"key":"19_CR19","doi-asserted-by":"crossref","unstructured":"Wu, L., Weaver, C., Austin, T.: CryptoManiac: A fast flexible architecture for secure communication. In: Proceedings of the 28th Annual International Symposium on Computer Architecture, pp. 110\u2013119. IEEE (2001)","DOI":"10.1145\/384285.379256"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-16214-0_19","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,27]],"date-time":"2023-01-27T19:44:23Z","timestamp":1674848663000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-16214-0_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319162133","9783319162140"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-16214-0_19","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"31 March 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}