{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T05:40:10Z","timestamp":1748497210191,"version":"3.41.0"},"publisher-location":"Cham","reference-count":20,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319198712"},{"type":"electronic","value":"9783319198729"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-19872-9_6","type":"book-chapter","created":{"date-parts":[[2015,7,14]],"date-time":"2015-07-14T13:05:16Z","timestamp":1436879116000},"page":"147-175","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Automatic Layout Optimizations for Integrated MOSFET Power Stages"],"prefix":"10.1007","author":[{"given":"David","family":"Guilherme","sequence":"first","affiliation":[]},{"given":"Jorge","family":"Guilherme","sequence":"additional","affiliation":[]},{"given":"Nuno","family":"Horta","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,7,15]]},"reference":[{"key":"6_CR1","doi-asserted-by":"crossref","unstructured":"Liew, B.K., Cheung, N.W., Hu, C.: Effects of self-heating on integrated circuit metallization lifetimes. In: IEDM Technical Digest., Washington, pp. 323\u2013326 (1989)","DOI":"10.1109\/IEDM.1989.74289"},{"issue":"1","key":"6_CR2","doi-asserted-by":"publisher","first-page":"17","DOI":"10.1109\/TDMR.2006.870340","volume":"6","author":"O Semenov","year":"2006","unstructured":"Semenov, O., Vassighi, A., Sachdev, M.: Impact of Self-Heating Effect on Long-Term Reliability and Performance Degradation in CMOS Circuits. IEEE Trans. Device Mater. Reliab. 6(1), 17\u201327 (2006)","journal-title":"IEEE Trans. Device Mater. Reliab."},{"key":"6_CR3","doi-asserted-by":"crossref","unstructured":"Tam, W.C., Blanton, S.: To DFM or not to DFM? In: IEEE Proceedings of the 48th Design Automation Conference, pp. 65\u201370, June 2011","DOI":"10.1145\/2024724.2024740"},{"key":"6_CR4","doi-asserted-by":"crossref","unstructured":"Tien, L.C., Tang, J.J., Chang, M.C.: An automatic layout generator for I\/O cells. In: Proceedings of the 5th International Workshop on System-on-Chip for Real-Time Applications, pp. 295\u2013300, July 2005","DOI":"10.1109\/IWSOC.2005.39"},{"key":"6_CR5","doi-asserted-by":"crossref","unstructured":"Ming, C., Na, B.: An efficient and flexible embedded memory IP compiler. In: Proceedings of International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 268\u2013273, Oct 2012","DOI":"10.1109\/CyberC.2012.52"},{"key":"6_CR6","doi-asserted-by":"crossref","unstructured":"Kelly, M., Servais, G., Diep, T., Lin, D., Twerefour, S., Shah, G.: A comparison of electrostatic discharge models and failure signatures for CMOS integrated circuit devices. In: Proceedings of the Electrical Overstress\/Electrostatic Discharge Symposium, pp. 175\u2013185, Sept 1995","DOI":"10.1109\/EOSESD.1995.478282"},{"issue":"10","key":"6_CR7","doi-asserted-by":"publisher","first-page":"245","DOI":"10.5194\/ars-6-245-2008","volume":"6","author":"E Franell","year":"2008","unstructured":"Franell, E., Drueen, S., Gossner, H., Schmitt-Landsiedel, D.: ESD full chip simulation: HBM and CDM requirements and simulation approach. Adv. Radio Sci. 6(10), 245\u2013251 (2008)","journal-title":"Adv. Radio Sci."},{"key":"6_CR8","doi-asserted-by":"publisher","first-page":"1143","DOI":"10.1057\/palgrave.jors.2602068","volume":"57","author":"B Suman","year":"2006","unstructured":"Suman, B., Kumar, P.: A survey of simulated annealing as a tool for single and multiobjective optimization. J. Oper. Res. Soc. 57, 1143\u20131160 (2006)","journal-title":"J. Oper. Res. Soc."},{"key":"6_CR9","unstructured":"Alpert, C.J., Mehta, D.P., Sapatnekar, S.S. (eds.): Handbook of algorithms for physical automation. CRC Press, Boca Raton. ISBN:10: 0849372429, ISBN:13: 978\u20130849372421 (2009)"},{"key":"6_CR10","doi-asserted-by":"crossref","unstructured":"Martins, R., Lourenco, N., Horta, N.: LAYGEN II\u2014automatic layout generation of analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11), 1641\u20131654 (2013)","DOI":"10.1109\/TCAD.2013.2269050"},{"issue":"1","key":"6_CR11","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1109\/24.488908","volume":"45","author":"P Lall","year":"1996","unstructured":"Lall, P.: Tutorial: temperature as an input to microelectronics\u2014reliability models. IEEE Trans. Reliab. 45(1), 3\u20139 (1996)","journal-title":"IEEE Trans. Reliab."},{"issue":"8","key":"6_CR12","doi-asserted-by":"publisher","first-page":"1487","DOI":"10.1109\/JPROC.2006.879797","volume":"94","author":"M Pedram","year":"2006","unstructured":"Pedram, M., Nazarian, S.: Thermal modeling, analysis, and management in VLSI circuits: principles and methods. Proc. IEEE 94(8), 1487\u20131501 (2006)","journal-title":"Proc. IEEE"},{"issue":"11","key":"6_CR13","doi-asserted-by":"publisher","first-page":"R17","DOI":"10.1088\/0960-1317\/15\/11\/R01","volume":"15","author":"T Bechtold","year":"2005","unstructured":"Bechtold, T., Rudnyi, E., Korvink, J.: Dynamic electro-thermal simulation of microsystems\u2014a review. J. Micromech. Microeng. 15(11), R17\u2013R31 (2005)","journal-title":"J. Micromech. Microeng."},{"issue":"4","key":"6_CR14","doi-asserted-by":"publisher","first-page":"566","DOI":"10.1109\/6144.974944","volume":"24","author":"W Batty","year":"2001","unstructured":"Batty, W., Christoffersen, C., Panks, A., David, S., Snowden, C., Steer, M.: Electrothermal CAD of power devices and circuits with fully physical time-dependent compact thermal modeling of complex nonlinear 3-d Systems. IEEE Trans. Compon. Packag. Technol. 24(4), 566\u2013590 (2001)","journal-title":"IEEE Trans. Compon. Packag. Technol."},{"issue":"2","key":"6_CR15","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1166\/jolpe.2007.128","volume":"3","author":"Y Han","year":"2007","unstructured":"Han, Y., Koren, I.: Simulated annealing based temperature aware floorplanning. J Low Power Electron. 3(2), 1\u201315 (2007)","journal-title":"J Low Power Electron."},{"key":"6_CR16","doi-asserted-by":"crossref","unstructured":"Ardestani, E., Ziabari, A., Shakouri, A., Renau, J.: Enabling power density and thermal-aware floorplanning. In: Proceeding of Semiconductor Thermal Measurement and Management Symposium, pp. 302\u2013307, Mar 2012","DOI":"10.1109\/STHERM.2012.6188864"},{"key":"6_CR17","doi-asserted-by":"crossref","unstructured":"Song, T., Sturcken, N., Athikulwongse, K., Shepard, K., Lim, S.K.: Thermal analysis and optimization of 2.5-D integrated voltage regulator. In: IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, pp. 25\u201328 (2012)","DOI":"10.1109\/EPEPS.2012.6457835"},{"key":"6_CR18","doi-asserted-by":"crossref","unstructured":"Ning, P., Wang, F., Ngo, K.D.T.: Automatic layout design for power module. IEEE Trans. Power Electron. 481\u2013487 (2013)","DOI":"10.1109\/TPEL.2011.2180739"},{"key":"6_CR19","doi-asserted-by":"crossref","unstructured":"Logan, S., Guthaus, M.R.: Fast thermal-aware floorplanning using white-space optimization. 17th IFIP International Conference on Very Large Scale Integration, pp. 65\u201370 (2009)","DOI":"10.1109\/VLSISOC.2009.6041332"},{"key":"6_CR20","doi-asserted-by":"crossref","unstructured":"Ng, W.T., Chang, M., Yoo, A., Langer, J., Hedquist, T., Schweiss, H.: High speed CMOS output stage for integrated DC-DC converters. In: Proceedings of 9th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1909\u20131912, Oct 2008","DOI":"10.1109\/ICSICT.2008.4734950"}],"container-title":["Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-19872-9_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T05:20:55Z","timestamp":1748496055000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-19872-9_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319198712","9783319198729"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-19872-9_6","relation":{},"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"15 July 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}