{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T05:40:10Z","timestamp":1748497210166,"version":"3.41.0"},"publisher-location":"Cham","reference-count":28,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319198712"},{"type":"electronic","value":"9783319198729"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-19872-9_8","type":"book-chapter","created":{"date-parts":[[2015,7,14]],"date-time":"2015-07-14T13:05:16Z","timestamp":1436879116000},"page":"217-248","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Nonlinearities Behavioral Modeling and Analysis of Pipelined ADC Building Blocks"],"prefix":"10.1007","author":[{"given":"Carlos","family":"Silva","sequence":"first","affiliation":[]},{"given":"Philippe","family":"Ayzac","sequence":"additional","affiliation":[]},{"given":"Nuno","family":"Horta","sequence":"additional","affiliation":[]},{"given":"Jorge","family":"Guilherme","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,7,15]]},"reference":[{"key":"8_CR1","doi-asserted-by":"crossref","unstructured":"Vital, J., Franca, J.: Synthesis of high-speed A\/D converter architectures with flexible functional simulation capabilities. In: Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2156\u20132159 (1992)","DOI":"10.1109\/ISCAS.1992.230565"},{"key":"8_CR2","doi-asserted-by":"crossref","unstructured":"Malcovati, P. et al.: Behavioral modeling of switched-capacitor sigma-delta modulators. In: IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol. 50, pp. 352\u2013364 (2003)","DOI":"10.1109\/TCSI.2003.808892"},{"key":"8_CR3","doi-asserted-by":"publisher","first-page":"1646","DOI":"10.1109\/TIM.2005.851085","volume":"54","author":"H Zare-Hoseini","year":"2005","unstructured":"Zare-Hoseini, H., Kale, I., Shoaei, O.: Modeling of switched-capacitor delta-sigma modulators in SIMULINK. IEEE Trans. Instrum. Meas. 54, 1646\u20131654 (2005)","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"Hamoui, A.A., Alhajj, T., Taherzadeh-Sani, M.: Behavioral modeling of opamp gain and dynamic effects for power optimization of delta-sigma modulators and pipelined ADCs. In: Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 330\u2013333 (2006)","DOI":"10.1109\/LPE.2006.4271859"},{"key":"8_CR5","doi-asserted-by":"publisher","first-page":"762","DOI":"10.1109\/4.391115","volume":"30","author":"F Medeiro","year":"1995","unstructured":"Medeiro, F., P\u00e9rez-Verd\u00fa, B., Rodr\u00edguez-V\u00e1zquez, A., Huertas, J.L.: A vertically integrated tool for automated design of sigma delta modulators. IEEE J. Solid-State Circuits 30, 762\u2013772 (1995)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"8_CR6","doi-asserted-by":"publisher","first-page":"1513","DOI":"10.1109\/82.746663","volume":"45","author":"J Goes","year":"1998","unstructured":"Goes, J., Vital, J.C., Franca, J.E.: Systematic design for optimization of high-speed self-calibrated pipelined A\/D converters. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process 45, 1513\u20131526 (1998)","journal-title":"IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process"},{"issue":"10","key":"8_CR7","doi-asserted-by":"publisher","first-page":"1116","DOI":"10.1109\/43.662675","volume":"16","author":"N Horta","year":"1997","unstructured":"Horta, N., Franca, J.: Algorithm-Driven Synthesis of Data Conversion Architectures. IEEE Trans. Comput. Aided Des 16(10), 1116\u20131135 (1997)","journal-title":"IEEE Trans. Comput. Aided Des"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"Horta, N., Franca, J., Leme, C.: Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1789\u20131782 (1991)","DOI":"10.1109\/ISCAS.1991.176751"},{"key":"8_CR9","unstructured":"Guilherme, J., Horta, N., Franca, J.: Symbolic synthesis of non-linear data converters. In: Proceedings of IEEE International Conference on Electronics Circuits and Systems (ICECS), vol. 3, pp. 219\u2013222 (1998)"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"Vital, J., Horta, N., Silva, N., Franca, J.: CATALYST: a highly flexible CAD tool for architecture-level design and analysis of data converters. In: Proceedings of Joint Conference European Design Automation Conference and European Application Specific Integrated Circuit (EDAC-EUROASIC), pp. 472\u2013477 (1993)","DOI":"10.1109\/EDAC.1993.386430"},{"key":"8_CR11","doi-asserted-by":"crossref","unstructured":"Horta, N., Fino, M., Goes, J.: Symbolic techniques applied to switched-current ADCs synthesis. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland, pp, 129\u2013132 (2000)","DOI":"10.1109\/ISCAS.2000.856013"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"Ruiz-Amaya, J. et al.: High-level synthesis of switched-capacitor, switched-current and continuous-time sigma-delta modulators using Simulink based time-domain behavioral models. IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 52, pp. 1795\u20131810 (2005)","DOI":"10.1109\/TCSI.2005.852479"},{"key":"8_CR13","unstructured":"Bilhan, E. et al.: Behavioral model of pipeline ADC by using SIMULINK. In: Proceedings of Southwest Symposium Mixed-Signal Design, pp. 147\u2013151 (2001)"},{"key":"8_CR14","doi-asserted-by":"crossref","unstructured":"Phelps, R. et al. Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19, 703\u2013717 (2000)","DOI":"10.1109\/43.848091"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"Ochotta, E., Carley, R.L.: Synthesis of high-performance analog circuits in ASTRX\/OBLX. IEEE Trans Comput. Aided Des. Integr. Circuits Syst. 15(3), 273\u2013294 (1996)","DOI":"10.1109\/43.489099"},{"key":"8_CR16","doi-asserted-by":"publisher","first-page":"549","DOI":"10.1109\/82.769803","volume":"46","author":"PTM Kwok","year":"1999","unstructured":"Kwok, P.T.M., Luong, H.C.: Power optimization for pipeline analog-to-digital converters. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 46, 549\u2013553 (1999)","journal-title":"IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process."},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Silva, C., Ayzac, P., Guilherme, J., Horta, N.: SCALES\u2014A behavioral simulator for pipelined analog-to-digital converter design. In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design\u2014SMAC, pp. 149\u2013152 (2012)","DOI":"10.1109\/SMACD.2012.6339439"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"Lee, S.H., Song, B.S.: Digital-domain calibration of multistep analog-to-digital converters. IEEE JSSC 27(12), 1679\u20131688 (1992)","DOI":"10.1109\/4.173093"},{"key":"8_CR19","unstructured":"James, C.: Clocking high-speed A\/D converters. National Semiconductors, App. Note 1558 (2007)"},{"key":"8_CR20","unstructured":"Andrea, B.: Analog-to-digital data converters. Universit\u00e1 degli Studi di Lecce. Lecture presentation, pp. 1\u2013322 (2007)"},{"key":"8_CR21","unstructured":"Mikael, G., Jacob, W., Nianxiong, T.: CMOS Data Converters for Communications, pp. 229\u2013256. Kluwer Academic Publishers, NY (2002) (ISBN 0-306-47305-4)"},{"issue":"4","key":"8_CR22","doi-asserted-by":"publisher","first-page":"443","DOI":"10.1109\/4.375965","volume":"30","author":"David Cline","year":"1995","unstructured":"Cline, David, Gray, Paul: A power optimized 13-bit 5 Msamples\/s pipelined analog to digital converter in 1.2\u00a0\u03bcm CMOS. IEEE J. Solid State Circuits 30(4), 443\u2013452 (1995)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"12","key":"8_CR23","doi-asserted-by":"publisher","first-page":"2077","DOI":"10.1109\/JSSC.2003.819168","volume":"38","author":"A Zanchi","year":"2003","unstructured":"Zanchi, A., Tsay, F., Papantonopoulos, I.: Impact of capacitor dielectric relaxation on a 14-bit 70MS\/s pipeline ADC in 3\u00a0V BiCMOS. IEEE J. Solid-State Circuits 38(12), 2077\u20132086 (2003)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"8_CR24","doi-asserted-by":"crossref","unstructured":"Doernberg, J., Lee, H.S., Hodges, D.A.: Full-speed testing of A\/D converters. IEEE J. Solid-State Circuits, SC-19(6), 820\u2013827 (1984)","DOI":"10.1109\/JSSC.1984.1052232"},{"key":"8_CR25","unstructured":"Schiff, M.: Spectrum analysis using digital FFT techniques. Agilent Technologies. AN106A (1997)"},{"key":"8_CR26","doi-asserted-by":"crossref","unstructured":"Sahoo, B.D., Razavi, B.: A fast simulator for pipelined A\/D converters. In: IEEE Circuits Syst. MWSCAS \u201909. (2), 402\u2013406 (2009)","DOI":"10.1109\/MWSCAS.2009.5236071"},{"key":"8_CR27","doi-asserted-by":"crossref","unstructured":"Navin, V., Hassoun, M., Ray, T., Marwan; Black, W., Lee, E., Soenen, E., Geiger, R.: A simulation environment for pipelined analog-to-digital converters. In: IEEE International Symposium on Circuits and Systems, pp. 1620\u20131623, 9\u201312 June 1997","DOI":"10.1109\/ISCAS.1997.621442"},{"key":"8_CR28","unstructured":"Zareba, G., Palusinski, O.: Behavioral simulator of analog-to-digital converters for telecommunication applications. In: Behavioral Modeling and Simulation Conference BMAS 2004, University of Arizona, pp. 1\u20136 (2004)"}],"container-title":["Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-19872-9_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T05:22:11Z","timestamp":1748496131000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-19872-9_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319198712","9783319198729"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-19872-9_8","relation":{},"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"15 July 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}