{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,7]],"date-time":"2025-02-07T11:10:23Z","timestamp":1738926623119,"version":"3.37.0"},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540959472"},{"type":"electronic","value":"9783540959489"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-540-95948-9_26","type":"book-chapter","created":{"date-parts":[[2009,1,31]],"date-time":"2009-01-31T15:58:14Z","timestamp":1233417494000},"page":"258-267","source":"Crossref","is-referenced-by-count":0,"title":["Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization"],"prefix":"10.1007","author":[{"given":"Nuno","family":"Dias","sequence":"first","affiliation":[]},{"given":"Marcelino","family":"Santos","sequence":"additional","affiliation":[]},{"given":"Floriberto","family":"Lima","sequence":"additional","affiliation":[]},{"given":"Beatriz","family":"Borges","sequence":"additional","affiliation":[]},{"given":"J\u00falio","family":"Paisana","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"26_CR1","doi-asserted-by":"crossref","unstructured":"Takayama, T., Maksimovic, D.: A power stage optimization method for monolithic DC-DC converters. In: IEEE Power Elec. Specialists Conf., PESC 2006. 37th IEEE, pp. 1\u20137 (2006)","DOI":"10.1109\/pesc.2006.1711765"},{"key":"26_CR2","doi-asserted-by":"crossref","unstructured":"Kursun, V., Narendra, S.G., De, V.K., Friedman, E.G.: Monolithic DC-DC Converter Analysis and MOSFET Gate Voltage Optimization. In: IEEE Fourth International Symposium on Quality Electronic Design, ISQED 2003, p. 279 (2003)","DOI":"10.1109\/ISQED.2003.1194746"},{"issue":"5","key":"26_CR3","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1109\/TCSII.2004.827557","volume":"51","author":"V. Kursun","year":"2004","unstructured":"Kursun, V., Narendra, S.G., De, V.K., Friedman, E.G.: Low-Voltage-Swing Monolithic DC-DC Conversion. IEEE Trans. on Circuits and Systems-II\u00a051(5) (May 2004)","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"26_CR4","doi-asserted-by":"crossref","unstructured":"Peterchev, A.V., Sanders, S.R.: Digital Loss-Minimizing Multi-Mode Synchronous Buck Converter Control. In: IEEE Power Electronics Specialists Conference, PESC 2004. 35th IEEE, vol. 5, pp. 3694\u20133699 (June 2004)","DOI":"10.1109\/PESC.2004.1355129"},{"issue":"1","key":"26_CR5","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/LPEL.2005.845177","volume":"3","author":"M.D. Mulligan","year":"2005","unstructured":"Mulligan, M.D., Broach, B., Lee, T.: A Constant-Frequency Method for Improving Light-Load Efficiency in Synchronous Buck Converters. IEEE Power Electronics Letters\u00a03(1), 24\u201329 (2005)","journal-title":"IEEE Power Electronics Letters"},{"key":"26_CR6","doi-asserted-by":"crossref","unstructured":"Mulligan, M.D., Broach, B., Lee, T.H.: A 3MHz Low-Voltage Buck Converter with Improved Light Load Efficiency. In: IEEE International Solid-State Circuits Conference, ISSCC 2007, pp. 528\u2013620 (February 2007)","DOI":"10.1109\/ISSCC.2007.373527"},{"key":"26_CR7","doi-asserted-by":"crossref","unstructured":"Musunuri, S., Chapman, P.L.: Optimization of CMOS Transistors for Low Power DC-DC Converters. In: IEEE Power Elect. Specialists Conf., PESC 2005. 36th IEEE, pp. 2151\u20132157 (2005)","DOI":"10.1109\/PESC.2005.1581930"},{"issue":"3","key":"26_CR8","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1109\/LPEL.2005.859769","volume":"3","author":"S. Musunuri","year":"2003","unstructured":"Musunuri, S., Chapman, P.L.: Improvement of Light-Load Efficiency Using Width-Switching Scheme for CMOS Transistors. IEEE Power Electronics Letters\u00a03(3), 105\u2013110 (2003)","journal-title":"IEEE Power Electronics Letters"},{"issue":"1","key":"26_CR9","doi-asserted-by":"publisher","first-page":"57","DOI":"10.1049\/iet-cds:20050331","volume":"1","author":"K.H. Chen","year":"2007","unstructured":"Chen, K.H., Chien, C.C., Hsu, C.H., Huang, L.R.: Optimum power-saving method for power MOSFET width of DC-DC converters. IET Circuits Devices & Systems\u00a01(1), 57\u201362 (2007)","journal-title":"IET Circuits Devices & Systems"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-95948-9_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,7]],"date-time":"2025-02-07T10:04:16Z","timestamp":1738922656000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-95948-9_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783540959472","9783540959489"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-95948-9_26","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}