{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,18]],"date-time":"2025-02-18T05:16:36Z","timestamp":1739855796783,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642118012"},{"type":"electronic","value":"9783642118029"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010]]},"DOI":"10.1007\/978-3-642-11802-9_9","type":"book-chapter","created":{"date-parts":[[2010,2,5]],"date-time":"2010-02-05T17:47:19Z","timestamp":1265392039000},"page":"46-55","source":"Crossref","is-referenced-by-count":1,"title":["Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis"],"prefix":"10.1007","author":[{"given":"Monica","family":"Figueiredo","sequence":"first","affiliation":[]},{"given":"Rui L.","family":"Aguiar","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"5","key":"9_CR1","doi-asserted-by":"publisher","first-page":"665","DOI":"10.1109\/5.929649","volume":"89","author":"E.G. Friedman","year":"2001","unstructured":"Friedman, E.G.: Clock distribution networks in synchronous digital integrated circuits. Proceedings of the IEEE\u00a089(5), 665\u2013692 (2001)","journal-title":"Proceedings of the IEEE"},{"issue":"4","key":"9_CR2","doi-asserted-by":"publisher","first-page":"565","DOI":"10.1109\/TCAD.2004.825875","volume":"23","author":"J.-L. Tsai","year":"2004","unstructured":"Tsai, J.-L., et al.: Zero skew clock-tree optimization with buffer insertion\/sizing and wire sizing. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems\u00a023(4), 565\u2013572 (2004)","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"9_CR3","doi-asserted-by":"publisher","first-page":"639","DOI":"10.1109\/TVLSI.2008.2000248","volume":"16","author":"A. Chakraborty","year":"2008","unstructured":"Chakraborty, A., et al.: Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. on VLSI Systems\u00a016, 639\u2013649 (2008)","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"9_CR4","doi-asserted-by":"crossref","unstructured":"Hashimoto, M., et al.: Statistical analysis of clock skew variation in H-tree structure. In: 6th Int. Symp. Qual. Elect. Design, March 2005, pp. 402\u2013407 (2005)","DOI":"10.1109\/ISQED.2005.114"},{"key":"9_CR5","doi-asserted-by":"crossref","unstructured":"Wason, V., et al.: An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. In: Int. Conf. on VLSI Design, January 2007, pp. 271\u2013277 (2007)","DOI":"10.1109\/VLSID.2007.33"},{"key":"9_CR6","doi-asserted-by":"crossref","unstructured":"Jang, J., et al.: Period Jitter Estimation in Global Clock Trees. In: 12th IEEE Workshop on Signal Propagation on Interconnects, May 12-15, pp. 1\u20134 (2008)","DOI":"10.1109\/SPI.2008.4558367"},{"issue":"3","key":"9_CR7","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1109\/TVLSI.2003.812310","volume":"11","author":"L.H. Chen","year":"2003","unstructured":"Chen, L.H., et al.: Buffer delay change in the presence of power and ground noise. IEEE Trans. on VLSI Systems\u00a011(3), 461\u2013473 (2003)","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"9_CR8","doi-asserted-by":"crossref","unstructured":"Samanta, R., et al.: Clock Buffer Polarity Assignment for Power Noise Reduction. In: IEEE\/ACM Int. Conf. on Computer-Aided Design, November 5-9, pp. 558\u2013562 (2006)","DOI":"10.1109\/ICCAD.2006.320174"},{"issue":"1","key":"9_CR9","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1109\/TCAD.2004.839471","volume":"24","author":"M. Badaroglu","year":"2005","unstructured":"Badaroglu, M., et al.: Digital ground bounce reduction by supply current shaping and clock frequency modulation. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems\u00a024(1), 65\u201376 (2005)","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"9_CR10","doi-asserted-by":"crossref","unstructured":"O\u2019Brien, P.R., Savarino, T.L.: Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation. In: IEEE Int. Conf. on Computer-Aided Design - ICCAD 1989, November 1989, pp. 512\u2013515 (1989)","DOI":"10.1109\/ICCAD.1989.77002"},{"key":"9_CR11","first-page":"790","volume":"34","author":"S.L.A. Hajimiri","year":"1999","unstructured":"Hajimiri, S.L.A., Lee, T.H.: Jitter and phase noise in ring oscillators. IEEE JSSC\u00a034, 790\u2013804 (1999)","journal-title":"IEEE JSSC"},{"key":"9_CR12","doi-asserted-by":"crossref","unstructured":"Tawfik, S.A., Kursun, V.: Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption. In: IEEE Int. Conf. on Electronics, Circuits and Systems, December 2007, pp. 845\u2013848 (2007)","DOI":"10.1109\/ICECS.2007.4511123"},{"key":"9_CR13","doi-asserted-by":"crossref","unstructured":"Mueller, J., Saleh, R.: Single Edge Clock Distribution for Improved Latency, Skew, and Jitter Performance. In: 21st Int. Conf. VLSI Design, January 4-8, pp. 214\u2013219 (2008)","DOI":"10.1109\/VLSI.2008.36"},{"key":"9_CR14","unstructured":"Osorio, J.F., et al.: Extraction of Circuit Elements for Macromodel-Based Estimation of Substrate Noise. In: XX Conf. Design Circ. Integrated Syst., pp. 1\u20136 (2005)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-11802-9_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,18]],"date-time":"2025-02-18T00:26:23Z","timestamp":1739838383000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-11802-9_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010]]},"ISBN":["9783642118012","9783642118029"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-11802-9_9","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2010]]}}}