{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:32:19Z","timestamp":1725661939987},"publisher-location":"Berlin, Heidelberg","reference-count":23,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783642282546"},{"type":"electronic","value":"9783642282553"}],"license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012]]},"DOI":"10.1007\/978-3-642-28255-3_50","type":"book-chapter","created":{"date-parts":[[2012,2,22]],"date-time":"2012-02-22T14:39:25Z","timestamp":1329921565000},"page":"453-464","source":"Crossref","is-referenced-by-count":1,"title":["Optimization-Based Design of Nano-CMOS LC-VCOs"],"prefix":"10.1007","author":[{"given":"Pedro","family":"Pereira","sequence":"first","affiliation":[]},{"given":"Helena","family":"Fino","sequence":"additional","affiliation":[]},{"given":"Fernando V.","family":"Coito","sequence":"additional","affiliation":[]},{"given":"M.","family":"Ventim-Neves","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"50_CR1","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/JETCAS.2011.2135470","volume":"1","author":"E. Maricau","year":"2011","unstructured":"Maricau, E., Gielen, G.: Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS. IEEE Journal on Emerging and Selected Topics in Circuits and Systems\u00a01, 50\u201358 (2011)","journal-title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems"},{"key":"50_CR2","doi-asserted-by":"publisher","first-page":"1339","DOI":"10.1109\/TVLSI.2008.2002046","volume":"17","author":"D. Ghai","year":"2009","unstructured":"Ghai, D., Mohanty, S., Kougianos, E.: Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a017, 1339\u20131342 (2009)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"50_CR3","doi-asserted-by":"crossref","unstructured":"Ghai, D., Mohanty, S., Kougianos, E.: Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. In: 9th International Symposium on Quality Electronic Design (ISQED), pp. 330\u2013333 (2008)","DOI":"10.1109\/ISQED.2008.4479750"},{"key":"50_CR4","doi-asserted-by":"crossref","unstructured":"Garitselov, O., Mohanty, S., Kougianos, E.: Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling. In: 12th International Symposium on Quality Electronic Design (ISQED), pp. 1\u20136 (2011)","DOI":"10.1109\/ISQED.2011.5770758"},{"key":"50_CR5","doi-asserted-by":"crossref","unstructured":"Murakami, R., Hara, S., Okada, K., Matsuzawa, A.: Design optimization of voltage controlled oscillators in consideration of parasitic capacitance. In: 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2009, pp. 1010\u20131013 (2009)","DOI":"10.1109\/MWSCAS.2009.5235972"},{"key":"50_CR6","unstructured":"Fard, A.: Analysis and Design of Low-Phase-Noise Integrated Voltage-Controlled Oscillators for Wide-Band RF Front-Ends. PhD Thesis, M\u00e4lardalen University, Department of Computer Science and Electronics, Institutionen f\u00f6r Datavetenskap och Elektronik, Sweden (2006)"},{"key":"50_CR7","doi-asserted-by":"crossref","unstructured":"Shah, D., Siva, K., Girishankar, G., Nagaaj, N.S.: Optimizing Interconnect for Performance in Standard Cell Library. In: Proc. IEEE Asian Pacific Conference on Circuits and Systems (2006)","DOI":"10.1109\/APCCAS.2006.342397"},{"key":"50_CR8","doi-asserted-by":"crossref","unstructured":"Ma, D., Shi, G., Lee, A.: A design platform for analog device size sensitivity analysis and visualization. In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 48\u201351 (2010)","DOI":"10.1109\/APCCAS.2010.5774855"},{"key":"50_CR9","doi-asserted-by":"crossref","unstructured":"Shi, G., Meng, X.: Variational analog integrated circuit design via symbolic sensitivity analysis. In: IEEE International Symposium on Circuits and System (ISCAS), pp. 3002\u20133005 (2009)","DOI":"10.1109\/ISCAS.2009.5118434"},{"key":"50_CR10","doi-asserted-by":"crossref","unstructured":"Gutierrez, I., Mel\u00e9ndez, J., Hern\u00e1ndez, E.: Design and Characterization of Integrated Varactors for RF Applications. John Wiley & Sons (2007)","DOI":"10.1002\/9780470035924"},{"key":"50_CR11","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1109\/JETCAS.2011.2135470","volume":"1","author":"E. Maricau","year":"2011","unstructured":"Maricau, E., Gielen, G.: Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS. IEEE Journal on Emerging and Selected Topics in Circuits and Systems\u00a01, 5\u201358 (2011)","journal-title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems"},{"key":"50_CR12","doi-asserted-by":"crossref","unstructured":"Nieuwoudt, A., Massoud, Y.: Robust automated synthesis methodology for integrated spiral inductors with variability. In: IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 502\u2013507 (2005)","DOI":"10.1109\/ICCAD.2005.1560119"},{"key":"50_CR13","doi-asserted-by":"publisher","first-page":"1953","DOI":"10.1109\/TCSI.2004.835691","volume":"51","author":"J. Park","year":"2004","unstructured":"Park, J., Choi, K., Allstot, D.: Parasitic-aware RF circuit design and optimization. IEEE Transactions on Circuits and Systems I: Regular Papers\u00a051, 1953\u20131966 (2004)","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"50_CR14","doi-asserted-by":"crossref","unstructured":"Murakami, R., Hara, S., Okada, K., Matsuzawa, A.: Design optimization of voltage controlled oscillators in consideration of parasitic capacitance. In: 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1010\u20131013 (2009)","DOI":"10.1109\/MWSCAS.2009.5235972"},{"key":"50_CR15","first-page":"517","volume-title":"Design of Integrated LC VCOs","author":"D. Ham","year":"2002","unstructured":"Ham, D.: Trade-Offs in Analog Circuit Design. In: Design of Integrated LC VCOs, pp. 517\u2013549. Springer, US (2002)"},{"key":"50_CR16","doi-asserted-by":"crossref","unstructured":"Fiorelli, R., Silveira, F., Peralas, E.: Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. In: 22nd Annual Symposium on Integrated Circuits and System Design (SBCCI), pp. 1\u20136 (2009)","DOI":"10.1145\/1601896.1601918"},{"key":"50_CR17","doi-asserted-by":"crossref","unstructured":"Ben Issa, D., Akacha, S., Kachouri, A., Samet, M.: Graphical optimization of 4GHz CMOS LC-VCO. In: 4th International Conference on Design Technology of Integrated Systems in Nanoscal Era (DTIS), pp. 33\u201337 (2009)","DOI":"10.1109\/DTIS.2009.4938019"},{"key":"50_CR18","doi-asserted-by":"crossref","unstructured":"Pereira, P., Helena Fino, M., Coito, F., Ventim-Neves, M.: RF integrated inductor modeling and its application to optimization-based design. J. Analog Integrated Circuits and Signal Processing (2011)","DOI":"10.1007\/s10470-011-9682-x"},{"key":"50_CR19","series-title":"IFIP AICT","doi-asserted-by":"publisher","first-page":"515","DOI":"10.1007\/978-3-642-11628-5_57","volume-title":"Emerging Trends in Technological Innovation","author":"P. Pereira","year":"2010","unstructured":"Pereira, P., Fino, M.H., Coito, F., Ventim-Neves, M.: GADISI \u2013 Genetic Algorithms Applied to the Automatic Design of Integrated Spiral Inductors. In: Camarinha-Matos, L.M., Pereira, P., Ribeiro, L. (eds.) DoCEIS 2010. IFIP AICT, vol.\u00a0314, pp. 515\u2013522. Springer, Heidelberg (2010)"},{"key":"50_CR20","doi-asserted-by":"crossref","unstructured":"Ma, D., Shi, G., Lee, A.: A design platform for analog device size sensitivity analysis and visualization. In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 48\u201351 (2010)","DOI":"10.1109\/APCCAS.2010.5774855"},{"key":"50_CR21","doi-asserted-by":"crossref","unstructured":"Li, X., Xu, H., Shi, G., Tai, A.: Hierarchical symbolic sensitivity computation with applications to large amplifier circuit design. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2733\u20132736 (2011)","DOI":"10.1109\/ISCAS.2011.5938170"},{"key":"50_CR22","doi-asserted-by":"crossref","unstructured":"Shi, G., Meng, X.: Variational analog integrated circuit design via symbolic sensitivity analysis. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3002\u20133005 (2009)","DOI":"10.1109\/ISCAS.2009.5118434"},{"key":"50_CR23","doi-asserted-by":"crossref","unstructured":"Pereira, P., Fino, H., Coito, F., Ventim-Neves, M.: ADISI- An efficient tool for the automatic design of integrated spiral inductors. In: 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 799\u2013802 (2009)","DOI":"10.1109\/ICECS.2009.5410776"}],"container-title":["IFIP Advances in Information and Communication Technology","Technological Innovation for Value Creation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-642-28255-3_50","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,20]],"date-time":"2024-04-20T06:21:49Z","timestamp":1713594109000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-642-28255-3_50"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"ISBN":["9783642282546","9783642282553"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/978-3-642-28255-3_50","relation":{},"ISSN":["1868-4238","1861-2288"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1861-2288"}],"subject":[],"published":{"date-parts":[[2012]]}}}