{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,23]],"date-time":"2024-12-23T04:40:02Z","timestamp":1734928802776,"version":"3.32.0"},"reference-count":63,"publisher":"Springer Science and Business Media LLC","issue":"2-3","license":[{"start":{"date-parts":[[1996,8,1]],"date-time":"1996-08-01T00:00:00Z","timestamp":838857600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[1996,8]]},"DOI":"10.1007\/bf01130409","type":"journal-article","created":{"date-parts":[[2005,2,6]],"date-time":"2005-02-06T14:22:27Z","timestamp":1107699747000},"page":"259-276","source":"Crossref","is-referenced-by-count":2,"title":["Techniques for power estimation and optimization at the logic level: A survey"],"prefix":"10.1007","volume":"13","author":[{"given":"Jos\u00e9","family":"Monteiro","sequence":"first","affiliation":[]},{"given":"Srinivas","family":"Devadas","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[1996,8,1]]},"reference":[{"key":"BF01130409_CR1","series-title":"Technical Report ERL M89\/44, Electronics Research Laboratory Report","volume-title":"The SPICE3 implementation guide","author":"T. Quarles","year":"1989","unstructured":"T. Quarles, \u201cThe SPICE3 implementation guide\u201d, Technical Report ERL M89\/44, Electronics Research Laboratory Report, University of California at Berkeley. Berkeley, California, April 1989."},{"key":"BF01130409_CR2","doi-asserted-by":"crossref","unstructured":"R. Tjarnstrom, \u201cPower dissipation estimate by switch level simulation\u201d, inProceedings of the IEEE International Symposium on Circuits and Systems, pp. 881\u2013884, May 1989.","DOI":"10.1109\/ISCAS.1989.100492"},{"key":"BF01130409_CR3","doi-asserted-by":"crossref","unstructured":"A. Salz and M. Horowitz, \u201cIRSIM: An incremental MOS switchlevel simulator\u201d, inProceedings of the 26th Design Automation Conference, pp. 173\u2013178, June 1989.","DOI":"10.1145\/74382.74412"},{"key":"BF01130409_CR4","unstructured":"L. Glasser and D. Dobberpuhl,The Design and Analysis of VLSI Circuits, Addison-Wesley, 1985."},{"issue":"No. 2","key":"BF01130409_CR5","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1109\/43.205010","volume":"12","author":"F. Najm","year":"1993","unstructured":"F. Najm, \u201cTransition density: A new measure of activity in digital circuits,IEEE Transactions on Computer-Aided Design, Vol. 12, No. 2, pp. 310\u2013323, Feb. 1993.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"issue":"No. 4","key":"BF01130409_CR6","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1109\/4.126534","volume":"27","author":"A. Chandrakasan","year":"1992","unstructured":"A. Chandrakasan, T. Sheng, and R.W. Brodersen, \u201cLow power CMOS digital design\u201d.Journal of Solid State Circuits, Vol. 27, No. 4, pp. 473\u2013484, April 1992.","journal-title":"Journal of Solid State Circuits"},{"key":"BF01130409_CR7","doi-asserted-by":"crossref","unstructured":"S. Devadas, K. Keutzer, and J. White, \u201cEstimation of power dissipation in CMOS combinational circuits using Boolean function manipulation\u201d, inIEEE Transactions on Computer-Aided Design, pp. 373\u2013383, March 1992.","DOI":"10.1109\/43.124424"},{"key":"BF01130409_CR8","doi-asserted-by":"crossref","unstructured":"S. Manne, A. Pardo, R. Bahar, G. Hachtel, F. Somenzi, E. Macii, and M. Poncino, \u201cComputing the maximum power cycles of a sequential circuit\u201d, inProceedings of the Design Automation Conference, pp. 23\u201328, June 1995.","DOI":"10.1145\/217474.217501"},{"issue":"No. 1","key":"BF01130409_CR9","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/92.219908","volume":"1","author":"R. Burch","year":"1993","unstructured":"R. Burch, F. Najm, P. Yang, and T. Trick, \u201cA Monte Carlo approach to power estimation,IEEE Transactions on VLSI Systems, Vol. 1, No. 1, pp. 63\u201371, March 1993.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"BF01130409_CR10","unstructured":"A. Papoulis,Probability, Random Variables and Stochastic Processes, McGraw-Hill, 3rd edition, 1991."},{"key":"BF01130409_CR11","doi-asserted-by":"crossref","unstructured":"M. Xakellis and F. Najm, \u201cStatistical estimation of the switching activity in digital circuits\u201d, inProceedings of the Design Automation Conference, pp. 728\u2013733, June 1994.","DOI":"10.1145\/196244.196628"},{"key":"BF01130409_CR12","doi-asserted-by":"crossref","unstructured":"A. Hill and S. Kang, \u201cDetermining accuracy bounds for simulation-based switching activity estimation\u201d, inInternational Symposium on Low Power Design, pp. 215\u2013220, April 1995.","DOI":"10.1145\/224081.224119"},{"issue":"No. 8","key":"BF01130409_CR13","doi-asserted-by":"crossref","first-page":"677","DOI":"10.1109\/TC.1986.1676819","volume":"35","author":"R. Bryant","year":"1986","unstructured":"R. Bryant, \u201cGraph-based algorithms for Boolean function manipulation\u201d,IEEE Transactions on Computers, Vol. C-35, No. 8, pp. 677\u2013691, Aug. 1986.","journal-title":"IEEE Transactions on Computers"},{"key":"BF01130409_CR14","doi-asserted-by":"crossref","unstructured":"A. Shen, S. Devadas, A. Ghosh, and K. Keutzer, \u201cOn average power dissipation and random pattern testability of combinational logic circuits\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 402\u2013407, Nov. 1992.","DOI":"10.1109\/ICCAD.1992.279338"},{"key":"BF01130409_CR15","doi-asserted-by":"crossref","unstructured":"M. Favalli and L. Benini, \u201cAnalysis of glitch power dissipation in CMOS ICs,\u201d inInternational Symposium on Low Power Design, pp. 123\u2013128, April 1995.","DOI":"10.1145\/224081.224103"},{"key":"BF01130409_CR16","unstructured":"M.A. Cirit, \u201cEstimating dynamic power consumption of CMOS circuits\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 534\u2013537, Nov. 1987."},{"key":"BF01130409_CR17","doi-asserted-by":"crossref","unstructured":"B. Kapoor, \u201cImproving the accuracy of circuit activity measurement\u201d, inProceedings of the 1994 International Workshop on Low Power Design, pp. 111\u2013116, April 1994.","DOI":"10.1145\/196244.196629"},{"issue":"No. 4","key":"BF01130409_CR18","doi-asserted-by":"crossref","first-page":"439","DOI":"10.1109\/43.45875","volume":"9","author":"F.N. Najm","year":"1990","unstructured":"F.N. Najm, R. Burch, P. Yang, and I. Hajj, \u201cProbabilistic simulation for reliability analysis of CMOS VLSI circuits\u201d,IEEE Transactions on Computer-Aided Design, Vol 9, No. 4, pp. 439\u2013450, April 1990.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"key":"BF01130409_CR19","doi-asserted-by":"crossref","unstructured":"C.Y. Tsui, M. Pedram, and A. Despain, \u201cEfficient estimation of dynamic power dissipation under a real delay model\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 224\u2013228, Nov. 1993.","DOI":"10.1109\/ICCAD.1993.580061"},{"key":"BF01130409_CR20","doi-asserted-by":"crossref","unstructured":"T. Uchino, F. Minami, T. Mitsuhashi, and N. Goto, \u201cSwitching activity analysis using boolean approximation method\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 20\u201325, Nov. 1995.","DOI":"10.1109\/ICCAD.1995.479880"},{"key":"BF01130409_CR21","unstructured":"A. Ghosh, S. Devadas, K. Keutzer, and J. White, \u201cEstimation of average switching activity in combinational and sequential circuits\u201d, inProceedings of the Design Automation Conference, pp. 253\u2013259, June 1992."},{"key":"BF01130409_CR22","unstructured":"P. Schneider and U. Schlichtmann, \u201cDecomposition of boolean functions for low power based on a new power estimation technique\u201d, inProceedings of the 1994 International Workshop on Low Power Design, pp. 123\u2013128, April 1994."},{"key":"BF01130409_CR23","doi-asserted-by":"crossref","unstructured":"G. Hachtel, E. Macii, A. Pardo, and F. Somenzi, \u201cProbabilistic analysis of large finite state machines\u201d, inProceedings of the Design Automation Conference, pp. 270\u2013275, June 1994.","DOI":"10.1145\/196244.196374"},{"key":"BF01130409_CR24","doi-asserted-by":"crossref","unstructured":"R. Bahar, E. Frohm, C. Gaona, G. Hachtel, E. Macii, A. Pardo, and F. Somenzi, \u201cAlgebraic decision diagrams and their applications\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 188\u2013191, Nov. 1993.","DOI":"10.1109\/ICCAD.1993.580054"},{"issue":"No. 3","key":"BF01130409_CR25","doi-asserted-by":"crossref","first-page":"404","DOI":"10.1109\/92.406998","volume":"3","author":"C.-Y. Tsui","year":"1995","unstructured":"C.-Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin, \u201cPower estimation for sequential logic circuits\u201d,IEEE Transactions on VLSI Systems, Vol. 3, No. 3, pp. 404\u2013416, Sept. 1995.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"BF01130409_CR26","doi-asserted-by":"crossref","unstructured":"F. Najm, S. Goel, and I. Hajj, \u201cPower estimation in sequential circuits\u201d, inProceedings of the Design Automation Conference, pp. 635\u2013640, June 1995.","DOI":"10.1145\/217474.217602"},{"key":"BF01130409_CR27","doi-asserted-by":"crossref","unstructured":"R. Marculescu, D. Marculescu, and M. Pedram, \u201cEfficient power estimation for highly correlated input streams\u201d, inProceedings of the Design Automation Conference, pp. 628\u2013634, June 1995.","DOI":"10.1145\/217474.217601"},{"key":"BF01130409_CR28","doi-asserted-by":"crossref","unstructured":"J. Monteiro and S. Devadas, \u201cTechniques for the power estimation of sequential logic circuits under user-specified input sequences and programs\u201d, inProceedings of the International Symposium on Low Power Design, pp. 33\u201338, April 1995.","DOI":"10.1145\/224081.224088"},{"issue":"No. 11","key":"BF01130409_CR29","doi-asserted-by":"crossref","first-page":"1621","DOI":"10.1109\/43.248073","volume":"12","author":"S. Sapatnekar","year":"1993","unstructured":"S. Sapatnekar, V. Rao, P. Vaidya, and S. Kang, \u201cAn exact solution to the transistor sizing problem for CMOS circuits using convex optimization\u201d,IEEE Transactions on Computer-Aided Design, Vol. 12, No. 11, pp. 1621\u20131634, Nov. 1993.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"key":"BF01130409_CR30","unstructured":"C.H. Tan and J. Allen, \u201cMinimization of power in VLSI circuits using transistor sizing, input ordering, and statistical power estimation\u201d, inProceedings of the International Workshop on Low Power Design, pp. 75\u201380, April 1994."},{"key":"BF01130409_CR31","doi-asserted-by":"crossref","unstructured":"R. Bahar, G. Hachtel, E. Macii, and F. Somenzi, \u201cA symbolic method to reduce power consumption of circuits containing false paths\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 368\u2013371, Nov. 1994.","DOI":"10.1109\/ICCAD.1994.629820"},{"key":"BF01130409_CR32","doi-asserted-by":"crossref","unstructured":"M. Borah, R. Owens, and M. Irwin, \u201cTransistor sizing for minimizing power consumption of CMOS circuits under delay constraint\u201d, inInternational Symposium on Low Power Design, pp. 167\u2013172, April 1995.","DOI":"10.1145\/224081.224111"},{"key":"BF01130409_CR33","doi-asserted-by":"crossref","unstructured":"M. Berkelaar and J. Jess, \u201cComputing the entire active area\/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 474\u2013480, Nov. 1994.","DOI":"10.1109\/ICCAD.1994.629853"},{"issue":"No. 4","key":"BF01130409_CR34","doi-asserted-by":"crossref","first-page":"408","DOI":"10.1109\/92.335010","volume":"2","author":"J. Cong","year":"1994","unstructured":"J. Cong and C. Koh, \u201cSimultaneous driver and wire sizing for performance and power optimization\u201d,IEEE Transactions on VLSI Systems, Vol. 2, No. 4, pp. 408\u2013425, Dec. 1994.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"BF01130409_CR35","doi-asserted-by":"crossref","unstructured":"L. Lavagno, P. McGeer, A. Saldanha, and A. Sangiovanni-Vincentelli, \u201cTimed shannon circuits: A power-efficient design style and synthesis tool\u201d, inProceedings of the Design Automation Conference, pp. 254\u2013260, June 1995.","DOI":"10.1145\/217474.217538"},{"key":"BF01130409_CR36","unstructured":"T. Kim, W. Burleson, and M. Ciesielski, \u201cLogic restructuring for wave-pipelined circuits\u201d, inProceedings of the International Workshop on Logic Synthesis, 1993."},{"key":"BF01130409_CR37","doi-asserted-by":"crossref","unstructured":"K. Bartlett, R.K. Brayton, G.D. Hachtel, R.M. Jacoby, C.R. Morrison, R.L. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, \u201cMulti-level logic minimization using implicit don't cares\u201d, inIEEE Transactions on Computer-Aided Design, pp. 723\u2013740, June 1988.","DOI":"10.1109\/43.3211"},{"key":"BF01130409_CR38","unstructured":"S. Iman and M. Pedram, \u201cMulti-level network optimization for low power\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 371\u2013377, Nov. 1994."},{"key":"BF01130409_CR39","unstructured":"R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, \u201cMIS: A multiple-level logic optimization system\u201d, inIEEE Transactions on Computer-Aided Design, pp. 1062\u20131081, Nov. 1987."},{"issue":"No. 4","key":"BF01130409_CR40","doi-asserted-by":"crossref","first-page":"503","DOI":"10.1109\/92.250198","volume":"1","author":"K. Roy","year":"1993","unstructured":"K. Roy and S. Prasad, \u201cCircuit activity based logic synthesis for low power reliable operations\u201d,IEEE Transactions on VLSI Systems, Vol. 1, No. 4, pp. 503\u2013513, Dec. 1993.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"BF01130409_CR41","unstructured":"R. Murgai, R. Brayton, and A. Sangiovanni-Vincentelli, \u201cDecomposition of logic functions for minimum transition activity\u201d, inProceedings of the 1994 International Workshop on Low Power Design, pp. 33\u201338, April 1994."},{"key":"BF01130409_CR42","doi-asserted-by":"crossref","unstructured":"S. Iman and M. Pedram, \u201cLogic extraction and factorization for low power\u201d, inProceedings of the Design Automation Conference, pp. 248\u2013253, June 1995.","DOI":"10.1145\/217474.217537"},{"key":"BF01130409_CR43","unstructured":"R. Panda and F. Najm, \u201cTechnology decomposition for lowpower synthesis\u201d, inProceedings of the Custom Integrated Circuit Conference, 1995."},{"key":"BF01130409_CR44","doi-asserted-by":"crossref","unstructured":"K. Keutzer, \u201cDAGON: Technology mapping and local optimization\u201d, inProceedings of the 24th Design Automation Conference, pp. 341\u2013347, June 1987.","DOI":"10.1145\/37888.37940"},{"key":"BF01130409_CR45","doi-asserted-by":"crossref","unstructured":"V. Tiwari, P. Ashar, and S. Malik, \u201cTechnology mapping for low power\u201d, inProceedings of the 30th Design Automation Conference, pp. 74\u201379, June 1993.","DOI":"10.1145\/157485.164581"},{"key":"BF01130409_CR46","doi-asserted-by":"crossref","unstructured":"C.-Y. Tsui, M. Pedram, and A.M. Despain, \u201cTechnology decomposition and mapping targeting low power dissipation\u201d, inProceedings of the 30th Design Automation Conference, pp. 68\u201373, June 1993.","DOI":"10.1145\/157485.164577"},{"key":"BF01130409_CR47","unstructured":"B. Lin, \u201cTechnology mapping for low power dissipation\u201d, inProceedings of the International Conference on Computer Design: VLSI in Computers and Processors, Oct. 1993."},{"key":"BF01130409_CR48","unstructured":"R. Bahar, H. Cho, G. Hachtel, E. Macii, and F. Somenzi, \u201cAn application of ADD-based timing analysis to combinational low power synthesis\u201d, inProceedings of the 1994 International Workshop on Low Power Design, pp. 39\u201344, April 1994."},{"key":"BF01130409_CR49","doi-asserted-by":"crossref","unstructured":"Y. Tamiya, Y. Matsunaga, and M. Fujita, \u201cLP-based cell selection with constraints of timing, area and power consumption\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 378\u2013381, Nov. 1994.","DOI":"10.1109\/ICCAD.1994.629822"},{"key":"BF01130409_CR50","volume-title":"Sequential Logic Synthesis","author":"P. Ashar","year":"1991","unstructured":"P. Ashar, S. Devadas, and A.R. Newton,Sequential Logic Synthesis, Kluwer Academic Publishers, Boston, Massachusetts, 1991."},{"key":"BF01130409_CR51","unstructured":"E. Olson and S. Kang, \u201cLow-power state assignment for finite state machines\u201d, inProceedings of the 1994 International Workshop on Low Power Design, pp. 63\u201368, April 1994."},{"key":"BF01130409_CR52","doi-asserted-by":"crossref","unstructured":"G. Hachtel, M. Hermida, A. Pardo, M. Poncino, and F. Somenzi, \u201cRe-encoding sequential circuits to reduce power dissipation\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 70\u201373, Nov. 1994.","DOI":"10.1109\/ICCAD.1994.629746"},{"key":"BF01130409_CR53","unstructured":"C.-Y. Tsui, M. Pedram, C.-A. Chen, and A.M. Despain, \u201cLow power state assignment targeting two- and multi-level logic implementations\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 82\u201387, Nov. 1994."},{"key":"BF01130409_CR54","unstructured":"M. Stan and W. Burleson, \u201cLimited-weight codes for low-power I\/O\u201d, inProceedings of the International Workshop on Low Power Design, pp. 209\u2013214, April 1994."},{"key":"BF01130409_CR55","doi-asserted-by":"crossref","unstructured":"W.A. Chren, \u201cLow delay-power product CMOS design using one-hot residue coding\u201d, inProceedings of the International Symposium on Low Power Design, April 1995.","DOI":"10.1145\/224081.224107"},{"key":"BF01130409_CR56","doi-asserted-by":"crossref","unstructured":"C.E. Leiserson, F.M. Rose, and J.B. Saxe, \u201cOptimizing synchronous circuitry by retiming\u201d, inProceedings of 3rd CalTech Conference on VLSI, pp. 23\u201336, March 1983.","DOI":"10.1007\/978-3-642-95432-0_7"},{"key":"BF01130409_CR57","doi-asserted-by":"crossref","unstructured":"S. Malik, E. Sentovich, R. Brayton, and A. Sangiovanni-Vincentelli, \u201cRetiming and resynthesis: Optimizing sequential circuits using combinational techniques\u201d, inIEEE Transactions on Computer-Aided Design, pp. 74\u201384, Jan. 1991.","DOI":"10.1109\/43.62793"},{"key":"BF01130409_CR58","doi-asserted-by":"crossref","unstructured":"J. Monteiro, S. Devadas, and A. Ghosh, \u201cRetiming sequential circuits for low power\u201d, inProceedings of the International Conference on Computer-Aided Design, pp. 398\u2013402, Nov. 1993.","DOI":"10.1109\/ICCAD.1993.580087"},{"key":"BF01130409_CR59","doi-asserted-by":"crossref","unstructured":"A. Chandrakasan,Low-Power Digital CMOS Design, Ph.D. Thesis, University of California at Berkeley, UCB\/ERL Memorandum No. M94\/65, Aug. 1994.","DOI":"10.1007\/978-1-4615-2325-3"},{"key":"BF01130409_CR60","doi-asserted-by":"crossref","unstructured":"L. Benini and G. De Micheli, \u201cTransformation and synthesis of FSMs for low power gated clock implementation\u201d, inProceedings of the International Symposium on Low Power Design, pp. 21\u201326, April 1995.","DOI":"10.1145\/224081.224086"},{"issue":"No. 4","key":"BF01130409_CR61","doi-asserted-by":"crossref","first-page":"426","DOI":"10.1109\/92.335011","volume":"2","author":"M. Alidina","year":"1994","unstructured":"M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, \u201cPrecomputation-based sequential logic optimization for low power\u201d,IEEE Transactions on VLSI Systems, Vol. 2, No. 4, pp. 426\u2013436, Dec. 1994.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"BF01130409_CR62","doi-asserted-by":"crossref","unstructured":"J. Monteiro, J. Rinderknecht, S. Devadas, and A. Ghosh, \u201cOptimization of combinational and sequential logic circuits for low power using precomputation\u201d, inProceedings of the 1995 Chapel Hill Conference on Advanced Research on VLSI, pp. 430\u2013444, March 1995.","DOI":"10.1109\/ARVLSI.1995.515637"},{"key":"BF01130409_CR63","doi-asserted-by":"crossref","unstructured":"V. Tiwari, P. Ashar, and S. Malik, \u201cGuarded evaluation: Pushing power management to logic synthesis\/design\u201d, inInternational Symposium on Low Power Design, pp. 221\u2013226, April 1995.","DOI":"10.1145\/224081.224120"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01130409.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF01130409\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01130409","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,23]],"date-time":"2024-12-23T03:47:17Z","timestamp":1734925637000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF01130409"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,8]]},"references-count":63,"journal-issue":{"issue":"2-3","published-print":{"date-parts":[[1996,8]]}},"alternative-id":["BF01130409"],"URL":"https:\/\/doi.org\/10.1007\/bf01130409","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[1996,8]]}}}