{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:08:46Z","timestamp":1767262126671,"version":"3.37.3"},"reference-count":89,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2017,7,18]],"date-time":"2017-07-18T00:00:00Z","timestamp":1500336000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100001827","name":"University of Amsterdam","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100001827","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Real-Time Syst"],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1007\/s11241-017-9285-4","type":"journal-article","created":{"date-parts":[[2017,7,18]],"date-time":"2017-07-18T05:51:10Z","timestamp":1500357070000},"page":"607-661","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":33,"title":["An extensible framework for multicore response time analysis"],"prefix":"10.1007","volume":"54","author":[{"given":"Robert I.","family":"Davis","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2487-7144","authenticated-orcid":false,"given":"Sebastian","family":"Altmeyer","sequence":"additional","affiliation":[]},{"given":"Leandro S.","family":"Indrusiak","sequence":"additional","affiliation":[]},{"given":"Claire","family":"Maiza","sequence":"additional","affiliation":[]},{"given":"Vincent","family":"Nelis","sequence":"additional","affiliation":[]},{"given":"Jan","family":"Reineke","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,7,18]]},"reference":[{"key":"9285_CR1","doi-asserted-by":"crossref","unstructured":"Alhammad A, Pellizzoni R (2014) Schedulability analysis of global memory-predictable scheduling. In: Proceedings of the international conference on embedded software (EMSOFT), pp 20:1\u201320:10","DOI":"10.1145\/2656045.2656070"},{"key":"9285_CR2","doi-asserted-by":"crossref","unstructured":"Alhammad A, Wasly S, Pellizzoni R (2015) Memory efficient global scheduling of real-time tasks. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 285\u2013296","DOI":"10.1109\/RTAS.2015.7108452"},{"key":"9285_CR3","unstructured":"Altmeyer S (2013) Analysis of preemptively scheduled hard real-time systems. epubli GmbH. \n                        http:\/\/www.ebay.de\/itm\/Analysis-of-Preemptively-Scheduled-Hard-Real-time-Systems-Sebastian-Altmeyer-\/142397905969"},{"key":"9285_CR4","doi-asserted-by":"crossref","unstructured":"Altmeyer S, Burgui\u00e8re C (2009) A new notion of useful cache block to improve the bounds of cache-related preemption delay. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 109\u2013118","DOI":"10.1109\/ECRTS.2009.21"},{"key":"9285_CR5","doi-asserted-by":"crossref","unstructured":"Altmeyer S, Davis RI, Maiza C (2011) Cache related pre-emption aware response time analysis for fixed priority pre-emptive systems. In: Proceedings of the real-time systems symposium (RTSS), pp 261\u2013271","DOI":"10.1109\/RTSS.2011.31"},{"issue":"5","key":"9285_CR6","doi-asserted-by":"crossref","first-page":"499","DOI":"10.1007\/s11241-012-9152-2","volume":"48","author":"S Altmeyer","year":"2012","unstructured":"Altmeyer S, Davis RI, Maiza C (2012) Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems. Real-Time Syst 48(5):499\u2013526","journal-title":"Real-Time Syst"},{"key":"9285_CR7","unstructured":"Altmeyer S, Douma R, Lunniss W, Davis RI (2014) Evaluation of cache partitioning for hard real-time systems. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 15\u201326"},{"key":"9285_CR8","doi-asserted-by":"crossref","unstructured":"Altmeyer S, Davis RI, Indrusiak L, Maiza C, Nelis V, Reineke J (2015) A generic and compositional framework for multicore response time analysis. In: Proceedings of the international conference on real time networks and systems (RTNS), pp 129\u2013138","DOI":"10.1145\/2834848.2834862"},{"key":"9285_CR9","doi-asserted-by":"publisher","unstructured":"Altmeyer S, Douma R, Lunniss W, Davis RI (2016) On the effectiveness of cache partitioning in hard real-time systems. Real-Time Syst. doi:\n                        10.1007\/s11241-015-9246-8","DOI":"10.1007\/s11241-015-9246-8"},{"key":"9285_CR10","unstructured":"Atanassov P, Puschner P (2001) Impact of DRAM refresh on the execution time of real-time tasks. In: IEEE international workshop on application of reliable computing and communication, pp 29\u201334"},{"key":"9285_CR11","doi-asserted-by":"crossref","first-page":"284","DOI":"10.1049\/sej.1993.0034","volume":"8","author":"N Audsley","year":"1993","unstructured":"Audsley N, Burns A, Richardson M, Tindell K, Wellings AJ (1993) Applying new scheduling theory to static priority pre-emptive scheduling. Softw Eng J 8:284\u2013292","journal-title":"Softw Eng J"},{"key":"9285_CR12","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1007\/BF00365393","volume":"3","author":"TP Baker","year":"1991","unstructured":"Baker TP (1991) Stack-based scheduling for realtime processes. Real-Time Syst 3:67\u201399","journal-title":"Real-Time Syst"},{"key":"9285_CR13","doi-asserted-by":"crossref","unstructured":"Baruah S, Burns A (2006) Sustainable scheduling analysis. In: Proceedings of the real-time systems symposium (RTSS), pp 159\u2013168","DOI":"10.1109\/RTSS.2006.47"},{"key":"9285_CR14","unstructured":"Bastoni A, Brandenburg B, Anderson J (2010) Cache-related preemption and migration delays: empirical approximation and impact on schedulability. In: Proceedings of the workshop on operating systems platforms for embedded real-time applications (OSPERT), pp 33\u201344"},{"key":"9285_CR15","doi-asserted-by":"crossref","unstructured":"Bertogna M, Cirinei M (2007) Response-time analysis for globally scheduled symmetric multiprocessor platforms. In: Proceedings of the Real-Time Systems Symposium (RTSS), pp 149\u2013160","DOI":"10.1109\/RTSS.2007.31"},{"issue":"5","key":"9285_CR16","doi-asserted-by":"crossref","first-page":"430","DOI":"10.1007\/s11241-011-9129-6","volume":"47","author":"B Bhat","year":"2011","unstructured":"Bhat B, Mueller F (2011) Making DRAM refresh predictable. Real-Time Syst 47(5):430\u2013453","journal-title":"Real-Time Syst"},{"key":"9285_CR17","doi-asserted-by":"crossref","first-page":"129","DOI":"10.1007\/s11241-005-0507-9","volume":"30","author":"E Bini","year":"2005","unstructured":"Bini E, Buttazzo G (2005) Measuring the performance of schedulability tests. Real-Time Syst 30:129\u2013154","journal-title":"Real-Time Syst"},{"issue":"2","key":"9285_CR18","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert N et al (2011) The gem5 simulator. SIGARCH Comput Archit News 39(2):1\u20137","journal-title":"SIGARCH Comput Archit News"},{"key":"9285_CR19","unstructured":"Blass T, Hahn S, Reineke J (2017) Write-back caches in WCET analysis. In: Proceedings of the euromicro conference on real-time systems (ECRTS)"},{"key":"9285_CR20","doi-asserted-by":"crossref","unstructured":"Bril RJ, Altmeyer S, van\u00a0den Heuvel MMHP, Davis RI, Behnam M (2014) Integrating cache-related pre-emption delays into analysis of fixed priority scheduling with pre-emption thresholds. In: Proceedings of the real-time systems symposium (RTSS), pp 161\u2013172","DOI":"10.1109\/RTSS.2014.25"},{"key":"9285_CR21","doi-asserted-by":"publisher","unstructured":"Bril RJ, Altmeyer S, van\u00a0den Heuvel MM, Davis RI, Behnam M (2017) Fixed priority scheduling with pre-emption thresholds and cache-related pre-emption delays: integrated analysis and evaluation. Real-Time Syst. doi:\n                        10.1007\/s11241-016-9266-z","DOI":"10.1007\/s11241-016-9266-z"},{"key":"9285_CR22","doi-asserted-by":"crossref","unstructured":"Bui D, Lee E, Liu I, Patel H, Reineke J (2011) Temporal isolation on multiprocessing architectures. In: Proceedings of the design automation conference (DAC), pp 274\u2013279","DOI":"10.1145\/2024724.2024787"},{"key":"9285_CR23","doi-asserted-by":"crossref","unstructured":"Burns A, Wellings AJ (2013) A schedulability compatible multiprocessor resource sharing protocol\u2014MRSP. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 282\u2013291","DOI":"10.1109\/ECRTS.2013.37"},{"key":"9285_CR24","unstructured":"Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proceedings of the international conference on hardware\/software codesign and system synthesis (CODES), pp 19\u201324"},{"key":"9285_CR25","doi-asserted-by":"crossref","unstructured":"Chattopadhyay S, Roychoudhury A, Mitra T (2010) Modeling shared cache and bus in multi-cores for timing analysis. In: Proceedings of the international workshop on software and compilers for embedded systems (SCOPES), pp 6:1\u20136:10","DOI":"10.1145\/1811212.1811220"},{"key":"9285_CR26","doi-asserted-by":"crossref","unstructured":"Choi J, Kang D, Ha S (2016) Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems. In: Proceedings of design, automation, and test in Europe (DATE), pp 181\u2013186","DOI":"10.3850\/9783981537079_0101"},{"issue":"3","key":"9285_CR27","doi-asserted-by":"crossref","first-page":"272","DOI":"10.1007\/s11241-015-9229-9","volume":"52","author":"D Dasari","year":"2016","unstructured":"Dasari D, Nelis V, Akesson B (2016) A framework for memory contention analysis in multi-core platforms. Real-Time Syst 52(3):272\u2013322","journal-title":"Real-Time Syst"},{"issue":"1","key":"9285_CR28","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1007\/s11241-010-9106-5","volume":"47","author":"RI Davis","year":"2010","unstructured":"Davis RI, Burns A (2010) Improved priority assignment for global fixed priority pre-emptive scheduling in multiprocessor real-time systems. Real-Time Syst 47(1):1\u201340","journal-title":"Real-Time Syst"},{"key":"9285_CR29","doi-asserted-by":"crossref","unstructured":"Davis RI, Burns A, Marinho J, Nelis V, Petters SM, Bertogna M (2013) Global fixed priority scheduling with deferred pre-emption. In: Proceedings of the international conference on embedded and real-time computing systems and applications (RTCSA), pp 1\u201311","DOI":"10.1109\/RTCSA.2013.6732198"},{"key":"9285_CR30","doi-asserted-by":"crossref","unstructured":"Davis RI, Burns A, Marinho J, Nelis V, Petters SM, Bertogna M (2015) Global and partitioned multiprocessor fixed priority scheduling with deferred preemption. ACM TECS 14(3):47:1\u201347:28","DOI":"10.1145\/2739954"},{"key":"9285_CR31","doi-asserted-by":"crossref","unstructured":"Davis RI, Altmeyer S, Reineke J (2016) Analysis of write-back caches under fixed-priority preemptive and non-preemptive scheduling. In: Proceedings of the international conference on real-time networks and systems (RTNS), pp 309\u2013318","DOI":"10.1145\/2997465.2997476"},{"key":"9285_CR32","doi-asserted-by":"crossref","unstructured":"Falk H, Kleinsorge J (2009) Optimal static WCET-aware scratchpad allocation of program code. In: Proceedings of the design automation conference (DAC), pp 732\u2013737","DOI":"10.1145\/1629911.1630101"},{"issue":"2\u20133","key":"9285_CR33","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1023\/A:1008186323068","volume":"17","author":"C Ferdinand","year":"1999","unstructured":"Ferdinand C, Wilhelm R (1999) Efficient and precise cache behavior prediction for real-time systems. Real-Time Syst 17(2\u20133):131\u2013181","journal-title":"Real-Time Syst"},{"issue":"2\u20133","key":"9285_CR34","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1016\/S0167-6423(99)00010-6","volume":"35","author":"C Ferdinand","year":"1999","unstructured":"Ferdinand C, Martin F, Wilhelm R, Alt M (1999) Cache behavior prediction by abstract interpretation. Sci Comput Program 35(2\u20133):163\u2013189","journal-title":"Sci Comput Program"},{"key":"9285_CR35","doi-asserted-by":"crossref","unstructured":"Gai P, Lipari G, Natale MD (2001) Minimizing memory utilization of real-time task sets in single and multi-processor systems-on-a-chip. In: Proceedings of the real-time systems symposium (RTSS), pp 73\u201383","DOI":"10.1109\/REAL.2001.990598"},{"key":"9285_CR36","unstructured":"Gustafsson J, Betts A, Ermedahl A, Lisper B (2010) The M\u00e4lardalen WCET benchmarks\u2014past, present and future. In: Proceedings of the international workshop on worst-case execution time analysis (WCET), pp 137\u2013147"},{"key":"9285_CR37","unstructured":"Gustavsson A, Ermedahl A, Lisper B, Pettersson P (2010) Towards WCET analysis of multicore architectures using UPPAAL. In: Proceedings of the international workshop on worst-case execution time analysis (WCET), pp 101\u2013112"},{"key":"9285_CR38","unstructured":"Hahn S, Reineke J, Wilhelm R (2013) Towards compositionality in execution time analysis\u2014definition and challenges. In: Proceedings of the international workshop on compositional theory and technology for real-time embedded systems (CRTS)"},{"key":"9285_CR39","doi-asserted-by":"crossref","unstructured":"Hahn S, Reineke J, Wilhelm R (2015) Toward compact abstractions for processor pipelines. In: Proceedings of the correct system design\u2014symposium in honor of Ernst-R\u00fcdiger Olderog on the occasion of his 60th birthday, pp 205\u2013220","DOI":"10.1007\/978-3-319-23506-6_14"},{"key":"9285_CR40","doi-asserted-by":"crossref","unstructured":"Hahn S, Jacobs M, Reineke J (2016) Enabling compositionality for multicore timing analysis. In: Proceedings of the international conference on real time and networks systems (RTNS)","DOI":"10.1145\/2997465.2997471"},{"key":"9285_CR41","doi-asserted-by":"crossref","unstructured":"Huang WH, Chen JJ, Reineke J (2016) MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources. In: Proceedings of the design automation conference (DAC), pp 1\u20136","DOI":"10.1145\/2897937.2898046"},{"key":"9285_CR42","doi-asserted-by":"crossref","unstructured":"Jacobs M, Hahn S, Hack S (2016) A framework for the derivation of WCET analyses for multi-core processors. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 141\u2013151","DOI":"10.1109\/ECRTS.2016.19"},{"issue":"5","key":"9285_CR43","doi-asserted-by":"crossref","first-page":"390","DOI":"10.1093\/comjnl\/29.5.390","volume":"29","author":"M Joseph","year":"1986","unstructured":"Joseph M, Pandya P (1986) Finding response times in a real-time system. Comput J 29(5):390\u2013395","journal-title":"Comput J"},{"key":"9285_CR44","doi-asserted-by":"crossref","unstructured":"Kelter T, Falk H, Marwedel P, Chattopadhyay S, Roychoudhury A (2011) Bus-aware multicore WCET analysis through TDMA offset bounds. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 3\u201312","DOI":"10.1109\/ECRTS.2011.9"},{"issue":"2","key":"9285_CR45","doi-asserted-by":"crossref","first-page":"185","DOI":"10.1007\/s11241-013-9189-x","volume":"50","author":"T Kelter","year":"2014","unstructured":"Kelter T, Falk H, Marwedel P, Chattopadhyay S, Roychoudhury A (2014) Static analysis of multi-core TDMA resource arbitration delays. Real-Time Syst J 50(2):185\u2013229","journal-title":"Real-Time Syst J"},{"key":"9285_CR46","doi-asserted-by":"crossref","unstructured":"Kim H, de\u00a0Niz D, Andersson B, Klein M, Mutlu O, Rajkumar R (2014a) Bounding memory interference delay in COTS-based multi-core systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 145\u2013154","DOI":"10.1109\/RTAS.2014.6925998"},{"key":"9285_CR47","doi-asserted-by":"crossref","unstructured":"Kim Y, Broman D, Cai J, Shrivastaval A (2014b) Wcet-aware dynamic code management on scratchpads for software-managed multicores. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 179\u2013188","DOI":"10.1109\/RTAS.2014.6926001"},{"issue":"3","key":"9285_CR48","doi-asserted-by":"crossref","first-page":"356","DOI":"10.1007\/s11241-016-9248-1","volume":"52","author":"H Kim","year":"2016","unstructured":"Kim H, de Niz D, Andersson B, Klein M, Mutlu O, Rajkumar R (2016) Bounding and reducing memory interference in cots-based multi-core systems. Real-Time Syst 52(3):356\u2013395","journal-title":"Real-Time Syst"},{"issue":"5\u20136","key":"9285_CR49","doi-asserted-by":"crossref","first-page":"736","DOI":"10.1007\/s11241-014-9211-y","volume":"50","author":"K Lampka","year":"2014","unstructured":"Lampka K, Giannopoulou G, Pellizzoni R, Wu Z, Stoimenov N (2014) A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets. Real-Time Syst 50(5\u20136):736\u2013773","journal-title":"Real-Time Syst"},{"issue":"6","key":"9285_CR50","doi-asserted-by":"crossref","first-page":"700","DOI":"10.1109\/12.689649","volume":"47","author":"CG Lee","year":"1998","unstructured":"Lee CG, Hahn J, Seo YM, Min S, Ha R, Hong S, Park CY, Lee M, Kim CS (1998) Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans Comput 47(6):700\u2013713","journal-title":"IEEE Trans Comput"},{"issue":"9","key":"9285_CR51","doi-asserted-by":"crossref","first-page":"805","DOI":"10.1109\/32.950317","volume":"27","author":"C Lee","year":"2001","unstructured":"Lee C, Lee K, Hahn J, Seo YM, Min SL, Ha R, Hong S, Park CY, Lee M, Kim CS (2001) Bounding cache-related preemption delay for real-time systems. IEEE Trans Softw Eng 27(9):805\u2013826","journal-title":"IEEE Trans Softw Eng"},{"key":"9285_CR52","unstructured":"Li YTS, Malik S (1995) Performance analysis of embedded software using implicit path enumeration. In: Proceedings of the design automation conference (DAC), pp 456\u2013461"},{"key":"9285_CR53","doi-asserted-by":"crossref","unstructured":"Li L, Mayer A (2016) Trace-based analysis methodology of program flash contention in embedded multicore systems. In: Proceedings of design, automation, and test in Europe (DATE), pp 199\u2013204","DOI":"10.3850\/9783981537079_0442"},{"key":"9285_CR54","doi-asserted-by":"crossref","unstructured":"Li Y, Suhendra V, Liang Y, Mitra T, Roychoudhury A (2009a) Timing analysis of concurrent programs running on shared cache multi-cores. In: Proceedings of the real-time systems symposium (RTSS), pp 57\u201367","DOI":"10.1109\/RTSS.2009.32"},{"key":"9285_CR55","doi-asserted-by":"crossref","unstructured":"Li Y, Suhendra V, Liang Y, Mitra T, Roychoudhury A (2009b) Timing analysis of concurrent programs running on shared cache multi-cores. In: Proceedings of the real-time systems symposium, pp 57\u201367","DOI":"10.1109\/RTSS.2009.32"},{"key":"9285_CR56","doi-asserted-by":"crossref","unstructured":"Liu I, Reineke J, Broman D, Zimmer M, Lee EA (2012) A PRET microarchitecture implementation with repeatable timing and competitive performance. In: Proceeedings of the international conference on computer design (ICCD), pp 87\u201393","DOI":"10.1109\/ICCD.2012.6378622"},{"key":"9285_CR57","doi-asserted-by":"crossref","unstructured":"Lu J, Bai K, Shrivastava A (2013) Ssdm: Smart stack data management for software managed multicores (SMMS). In: Proceedings of the design automation conference (DAC), pp 1\u20138","DOI":"10.1145\/2463209.2488918"},{"key":"9285_CR58","doi-asserted-by":"crossref","unstructured":"Lundqvist T, Stenstr\u00f6m P (1999) Timing anomalies in dynamically scheduled microprocessors. In: Proceedings of the real-time systems symposium (RTSS), pp 12\u201321","DOI":"10.1109\/REAL.1999.818824"},{"key":"9285_CR59","doi-asserted-by":"crossref","unstructured":"Lunniss W, Altmeyer S, Davis RI (2012) Optimising task layout to increase schedulability via reduced cache related pre-emption delays. In: Proceedings of the international conference on real-time networks and systems (RTNS), pp 161\u2013170","DOI":"10.1145\/2392987.2393008"},{"key":"9285_CR60","doi-asserted-by":"crossref","unstructured":"Lunniss W, Altmeyer S, Maiza C, Davis R (2013) Integrating cache related pre-emption delay analysis into EDF scheduling. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 75\u201384","DOI":"10.1109\/RTAS.2013.6531081"},{"key":"9285_CR61","doi-asserted-by":"crossref","unstructured":"Lv M, Yi W, Guan N, Yu G (2010) Combining abstract interpretation with model checking for timing analysis of multicore software. In: Proceedings of the real-time systems symposium (RTSS), pp 339\u2013349","DOI":"10.1109\/RTSS.2010.30"},{"key":"9285_CR62","doi-asserted-by":"crossref","unstructured":"Mancuso R, Dudko R, Betti E, Cesati M, Caccamo M, Pellizzoni R (2013) Real-time cache management framework for multi-core architectures. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 45\u201354","DOI":"10.1109\/RTAS.2013.6531078"},{"key":"9285_CR63","doi-asserted-by":"crossref","unstructured":"Melani A, Bertogna M, Bonifaci V, Marchetti-Spaccamela A, Buttazzo G (2015) Memory-processor co-scheduling in fixed priority systems. In: Proceedings of the international conference on real-time networks and systems (RTNS), pp 87\u201396","DOI":"10.1145\/2834848.2834854"},{"key":"9285_CR64","doi-asserted-by":"publisher","unstructured":"Melani A, Bertogna M, Davis RI, Bonifaci V, Marchetti-Spaccamela A, Buttazzo G (2016) Exact response time analysis for fixed priority memory-processor co-scheduling. IEEE Trans Comput. doi:\n                        10.1109\/TC.2016.2614819","DOI":"10.1109\/TC.2016.2614819"},{"key":"9285_CR65","unstructured":"Micron Technologies, Inc (1999) Various methods of DRAM refresh. Tech. rep"},{"key":"9285_CR66","unstructured":"Muliadi L (1999) Discrete event modeling in ptolemy II. Master\u2019s report, University of California, Berkeley. \n                        http:\/\/ptolemy.eecs.berkeley.edu\/publications\/papers\/99\/deModeling\/"},{"key":"9285_CR67","doi-asserted-by":"crossref","unstructured":"Nowotsch J, Paulitsch M, Buhler D, Theiling H, Wegener S, Schmidt M (2014) Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 109\u2013118","DOI":"10.1109\/ECRTS.2014.20"},{"issue":"3","key":"9285_CR68","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1145\/1555815.1555764","volume":"37","author":"M Paolieri","year":"2009","unstructured":"Paolieri M, Qui\u00f1ones E, Cazorla FJ, Bernat G, Valero M (2009) Hardware support for WCET analysis of hard real-time multicore systems. SIGARCH Comput Archit News 37(3):57\u201368","journal-title":"SIGARCH Comput Archit News"},{"key":"9285_CR69","unstructured":"Paolieri M, Qui\u00f1ones E, Cazorla FJ, Davis RI, Valero M (2011) Ia\n                        $${\\hat{}}$$\n                        \n                            \n                                \n                                    \n                                    ^\n                                \n                            \n                        \n                     3: An interference aware allocation algorithm for multicore hard real-time systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 280\u2013290"},{"key":"9285_CR70","doi-asserted-by":"crossref","unstructured":"Pellizzoni R, Schranzhofer A, Chen JJ, Caccamo M, Thiele L (2010) Worst case delay analysis for memory interference in multicore systems. In: Proceedings of design automation and test in Europe (DATE), pp 741\u2013746","DOI":"10.1109\/DATE.2010.5456952"},{"key":"9285_CR71","doi-asserted-by":"crossref","unstructured":"Pellizzoni R, Betti E, Bak S, Criswell J, Caccamo M, Kegley R (2011) A predictable execution model for COTS-based embedded systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 269\u2013279","DOI":"10.1109\/RTAS.2011.33"},{"issue":"4","key":"9285_CR72","first-page":"34","volume":"8","author":"P Radojkovi\u0107","year":"2012","unstructured":"Radojkovi\u0107 P, Girbal S, Grasset A, Qui\u00f1ones E, Yehia S, Cazorla FJ (2012) On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. ACM TACO 8(4):34","journal-title":"ACM TACO"},{"key":"9285_CR73","doi-asserted-by":"publisher","unstructured":"Reineke J, Doerfert J (2014) Architecture-parametric timing analysis. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 189\u2013200. doi:\n                        10.1109\/RTAS.2014.6926002","DOI":"10.1109\/RTAS.2014.6926002"},{"key":"9285_CR74","doi-asserted-by":"crossref","unstructured":"Rihani H, Moy M, Maiza C, Davis RI, Altmeyer S (2016) Response time analysis of synchronous data flow programs on a many-core processor. In: Proceedings of the international conference on real-time networks and systems (RTNS), ACM, pp 67\u201376","DOI":"10.1145\/2997465.2997472"},{"key":"9285_CR75","doi-asserted-by":"crossref","unstructured":"Rosen J, Andrei A, Eles P, Peng Z (2007) Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In: proceedings of the real-time systems symposium (RTSS), pp 49\u201360","DOI":"10.1109\/RTSS.2007.24"},{"key":"9285_CR76","doi-asserted-by":"crossref","unstructured":"Schliecker S, Negrean M, Ernst R (2010) Bounding the shared resource load for the performance analysis of multiprocessor systems. In: Proceedings of the design automation conference (DAC), pp 759\u2013764","DOI":"10.1109\/DATE.2010.5456951"},{"key":"9285_CR77","doi-asserted-by":"crossref","unstructured":"Schranzhofer A, Chen JJ, Thiele L (2010) Timing analysis for TDMA arbitration in resource sharing systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 215\u2013224","DOI":"10.1109\/RTAS.2010.24"},{"key":"9285_CR78","doi-asserted-by":"crossref","unstructured":"Schranzhofer A, Pellizzoni R, Chen JJ, Thiele L, Caccamo M (2011) Timing analysis for resource access interference on adaptive resource arbiters. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 213\u2013222","DOI":"10.1109\/RTAS.2011.28"},{"key":"9285_CR79","doi-asserted-by":"crossref","unstructured":"Slijepcevic M, Kosmidis L, Abella J, Quiones E, Cazorla FJ (2014) Time-analysable non-partitioned shared caches for real-time multicore systems. In: Proceedings of the design automation conference (DAC), pp 1\u20136","DOI":"10.1145\/2593069.2593235"},{"key":"9285_CR80","doi-asserted-by":"crossref","unstructured":"Trilla D, Jalle J, Fernandez M, Abella J, Cazorla FJ (2016) Improving early design stage timing modeling in multicore based real-time systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 1\u201312","DOI":"10.1109\/RTAS.2016.7461338"},{"key":"9285_CR81","doi-asserted-by":"crossref","unstructured":"Valsan PK, Yun H, Farshchi F (2016) Taming non-blocking caches to improve isolation in multicore real-time systems. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 1\u201312","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"9285_CR82","unstructured":"Ward BC, Herman JL, Kenna CJ, Anderson JH (2013) Making shared caches more predictable on multicore platforms. In: Proceedings of the euromicro conference on real-time systems, pp 157\u2013167"},{"key":"9285_CR83","doi-asserted-by":"crossref","unstructured":"Wasly S, Pellizzoni R (2014) Hiding memory latency using fixed priority scheduling. In: Proceedings of the IEEE real-time and embedded technology and applications symposium (RTAS), pp 75\u201386","DOI":"10.1109\/RTAS.2014.6925992"},{"key":"9285_CR84","doi-asserted-by":"crossref","unstructured":"Whitham J, Davis RI, Audsley N, Altmeyer S, Maiza C (2012) Investigation of scratchpad memory for preemptive multitasking. In: Proceedings of the real-time systems symposium (RTSS), pp 3\u201313","DOI":"10.1109\/RTSS.2012.54"},{"key":"9285_CR85","doi-asserted-by":"crossref","unstructured":"Whitham J, Audsley N, Davis RI (2014) Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system. ACM Trans Embed Comput Syst 13(4s):120:1\u2013120:25","DOI":"10.1145\/2523070"},{"key":"9285_CR86","doi-asserted-by":"crossref","unstructured":"Yan J, Zhang W (2008) WCET analysis for multi-core processors with shared L2 instruction caches. In: Proceedings of the real-time and embedded technology and applications symposium (RTAS), pp 80\u201389","DOI":"10.1109\/RTAS.2008.6"},{"issue":"6","key":"9285_CR87","doi-asserted-by":"crossref","first-page":"681","DOI":"10.1007\/s11241-012-9158-9","volume":"48","author":"G Yao","year":"2012","unstructured":"Yao G, Pellizzoni R, Bak S, Betti E, Caccamo M (2012) Memory-centric scheduling for multicore hard real-time systems. Real-Time Syst J 48(6):681\u2013715","journal-title":"Real-Time Syst J"},{"key":"9285_CR88","doi-asserted-by":"crossref","unstructured":"Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2012) Memory access control in multiprocessor for real-time systems with mixed criticality. In: Proceedings of the euromicro conference on real-time systems (ECRTS), pp 299\u2013308","DOI":"10.1109\/ECRTS.2012.32"},{"key":"9285_CR89","doi-asserted-by":"crossref","unstructured":"Yun H, Pellizzoni R, Valsan PK (2015) Parallelism-aware memory interference delay analysis for COTS multicore systems. In: Proceedings of the euromicro conference on real-time Systems, pp 184\u2013195","DOI":"10.1109\/ECRTS.2015.24"}],"container-title":["Real-Time Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11241-017-9285-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11241-017-9285-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11241-017-9285-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,6,30]],"date-time":"2018-06-30T05:46:40Z","timestamp":1530337600000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11241-017-9285-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7,18]]},"references-count":89,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,7]]}},"alternative-id":["9285"],"URL":"https:\/\/doi.org\/10.1007\/s11241-017-9285-4","relation":{},"ISSN":["0922-6443","1573-1383"],"issn-type":[{"type":"print","value":"0922-6443"},{"type":"electronic","value":"1573-1383"}],"subject":[],"published":{"date-parts":[[2017,7,18]]}}}