{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T15:25:12Z","timestamp":1649172312491},"reference-count":14,"publisher":"Elsevier BV","issue":"10","license":[{"start":{"date-parts":[[1990,12,1]],"date-time":"1990-12-01T00:00:00Z","timestamp":660009600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computer-Aided Design"],"published-print":{"date-parts":[[1990,12]]},"DOI":"10.1016\/0010-4485(90)90009-2","type":"journal-article","created":{"date-parts":[[2003,3,14]],"date-time":"2003-03-14T09:47:17Z","timestamp":1047635237000},"page":"618-632","source":"Crossref","is-referenced-by-count":0,"title":["MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach"],"prefix":"10.1016","volume":"22","author":[{"given":"Jin-Hyeung","family":"Kong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen A.","family":"Szygenda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0010-4485(90)90009-2_BIB1","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/C-M.1975.218898","article-title":"Digital logic simulator in a time based, table-driven environment, part-1: Design verification","volume":"Vol 8","author":"Szygenda","year":"1975","journal-title":"Computer"},{"key":"10.1016\/0010-4485(90)90009-2_BIB2","doi-asserted-by":"crossref","first-page":"160","DOI":"10.1109\/TC.1984.1676408","article-title":"A switch-level model and simulator for MOS digital systems","volume":"Vol C-33","author":"Bryant","year":"1984","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0010-4485(90)90009-2_BIB3","doi-asserted-by":"crossref","first-page":"602","DOI":"10.1109\/TC.1986.1676801","article-title":"Pseudo-Boolean logic circuits","author":"Hayes","year":"1986","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0010-4485(90)90009-2_BIB4","series-title":"IEEE Proc. ICCD","first-page":"437","article-title":"RSIM \u2014 a logic-level timing simulator","author":"Terman","year":"1983"},{"key":"10.1016\/0010-4485(90)90009-2_BIB5","doi-asserted-by":"crossref","first-page":"193","DOI":"10.1109\/TCAD.1983.1270036","article-title":"Local relaxation algorithms for event-driven simulation of MOS networks including assignable delay modeling","volume":"Vol CAD-2","author":"Dumlugol","year":"1983","journal-title":"IEEE Trans. Computer-Aided Des."},{"key":"10.1016\/0010-4485(90)90009-2_BIB6","series-title":"Proc. 25th Design Automation Conf.","first-page":"506","article-title":"A dynamically-directed switch model for MOS logic simulation","author":"Adler","year":"1988"},{"key":"10.1016\/0010-4485(90)90009-2_BIB7","series-title":"Proc. 20th Design Automation Conf.","first-page":"100","article-title":"BIMOS, an MOS oriented multi-level logic simulator","author":"Stevens","year":"1983"},{"key":"10.1016\/0010-4485(90)90009-2_BIB8","series-title":"IEEE Proc. ICCAD","first-page":"200","article-title":"A logic simulation technique for gate\/transistor level circuits with precise delay estimation","author":"Eguchi","year":"1985"},{"key":"10.1016\/0010-4485(90)90009-2_BIB9","doi-asserted-by":"crossref","first-page":"282","DOI":"10.1109\/TCAD.1987.1270272","article-title":"Fully dynamic switch-level simulation of CMOS circuits","volume":"Vol CAD-6","author":"Sundblad","year":"1987","journal-title":"IEEE Trans. Comput.-Aided Des."},{"key":"10.1016\/0010-4485(90)90009-2_BIB10","series-title":"Proc. International Test Conf.","first-page":"340","article-title":"Automatic modeling of MOS transistor networks for test pattern generation","author":"Vivier","year":"1986"},{"key":"10.1016\/0010-4485(90)90009-2_BIB11","series-title":"Digital logic and computer design","author":"Mano","year":"1979"},{"key":"10.1016\/0010-4485(90)90009-2_BIB12","doi-asserted-by":"crossref","first-page":"336","DOI":"10.1109\/TCAD.1985.1270130","article-title":"A switch-level timing verifier for digital MOS VLSI","author":"Ousterhout","year":"1985","journal-title":"IEEE Trans. Comput.-Aided Des."},{"key":"10.1016\/0010-4485(90)90009-2_BIB13","series-title":"ERL Memo ERL-M520","article-title":"SPICE2: a computer program to simulate semiconductor circuits","author":"Nagel","year":"1975"},{"key":"10.1016\/0010-4485(90)90009-2_BIB14","series-title":"Proc. 17th Design Automation Conf.","first-page":"610","article-title":"A multiple delay simulator for LSI circuits","author":"Nham","year":"1980"}],"container-title":["Computer-Aided Design"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0010448590900092?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0010448590900092?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,26]],"date-time":"2019-03-26T15:59:44Z","timestamp":1553615984000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0010448590900092"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990,12]]},"references-count":14,"journal-issue":{"issue":"10","published-print":{"date-parts":[[1990,12]]}},"alternative-id":["0010448590900092"],"URL":"https:\/\/doi.org\/10.1016\/0010-4485(90)90009-2","relation":{},"ISSN":["0010-4485"],"issn-type":[{"value":"0010-4485","type":"print"}],"subject":[],"published":{"date-parts":[[1990,12]]}}}