{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T09:07:23Z","timestamp":1648804043153},"reference-count":4,"publisher":"Elsevier BV","issue":"1","license":[{"start":{"date-parts":[[1984,1,1]],"date-time":"1984-01-01T00:00:00Z","timestamp":441763200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Information Processing Letters"],"published-print":{"date-parts":[[1984,1]]},"DOI":"10.1016\/0020-0190(84)90074-7","type":"journal-article","created":{"date-parts":[[2002,7,26]],"date-time":"2002-07-26T04:20:15Z","timestamp":1027657215000},"page":"47-49","source":"Crossref","is-referenced-by-count":1,"title":["Large processors are good in VLSI chips"],"prefix":"10.1016","volume":"18","author":[{"given":"Xiaolong","family":"Jin","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0020-0190(84)90074-7_BIB1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/SFCS.1981.22","article-title":"New lower bound technique for VLSI","author":"Leighton","year":"1981","journal-title":"Proc. 22nd Ann. IEEE Symp. on Foundations of Computer Science"},{"key":"10.1016\/0020-0190(84)90074-7_BIB2","first-page":"85","article-title":"A layout strategy for VLSI which is provably good","author":"Leighton","year":"1982","journal-title":"Proc. 14th ACM Symp. on Theory of Computing"},{"key":"10.1016\/0020-0190(84)90074-7_BIB3","first-page":"270","article-title":"Area-efficient graph layouts (for VLSI)","author":"Leiserson","year":"1980","journal-title":"Proc. 21st Ann. Symp. on Foundations of Computer Science"},{"key":"10.1016\/0020-0190(84)90074-7_BIB4","doi-asserted-by":"crossref","first-page":"177","DOI":"10.1137\/0136016","article-title":"A separator theorem for planar graphs","volume":"36","author":"Lipton","year":"1979","journal-title":"SIAM J. Appl. Math."}],"container-title":["Information Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0020019084900747?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0020019084900747?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,12]],"date-time":"2019-04-12T12:53:01Z","timestamp":1555073581000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0020019084900747"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1984,1]]},"references-count":4,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1984,1]]}},"alternative-id":["0020019084900747"],"URL":"https:\/\/doi.org\/10.1016\/0020-0190(84)90074-7","relation":{},"ISSN":["0020-0190"],"issn-type":[{"value":"0020-0190","type":"print"}],"subject":[],"published":{"date-parts":[[1984,1]]}}}