{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,10]],"date-time":"2025-09-10T22:46:45Z","timestamp":1757544405973},"reference-count":9,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1981,4,1]],"date-time":"1981-04-01T00:00:00Z","timestamp":354931200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2013,7,17]],"date-time":"2013-07-17T00:00:00Z","timestamp":1374019200000},"content-version":"vor","delay-in-days":11795,"URL":"https:\/\/www.elsevier.com\/open-access\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Computer and System Sciences"],"published-print":{"date-parts":[[1981,4]]},"DOI":"10.1016\/0022-0000(81)90029-5","type":"journal-article","created":{"date-parts":[[2003,12,4]],"date-time":"2003-12-04T12:01:00Z","timestamp":1070539260000},"page":"230-242","source":"Crossref","is-referenced-by-count":27,"title":["Area\u2014time tradeoffs for matrix multiplication and related problems in VLSI models"],"prefix":"10.1016","volume":"22","author":[{"given":"John E.","family":"Savage","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"year":"1979","series-title":"Introduction to VLSI Systems","author":"Mead","key":"10.1016\/0022-0000(81)90029-5_BIB1"},{"key":"10.1016\/0022-0000(81)90029-5_BIB2","series-title":"Proc. Ilth Annual ACM Symposium on Theory of Computing","first-page":"81","article-title":"Area-Time Complexity for VLSI","author":"Thompson","year":"1979"},{"article-title":"A Complexity Theory for VLSI","year":"1980","author":"Thompson","key":"10.1016\/0022-0000(81)90029-5_BIB3"},{"article-title":"The Area-Time Complexity of Binary Multiplication","year":"1979","author":"Brent","key":"10.1016\/0022-0000(81)90029-5_BIB4"},{"key":"10.1016\/0022-0000(81)90029-5_BIB5","unstructured":"H. T. Kung and C. E. Leiserson, \u201cSystolic Arrays for VLSI,\u201d in [1]."},{"key":"10.1016\/0022-0000(81)90029-5_BIB6","doi-asserted-by":"crossref","first-page":"77","DOI":"10.1016\/0020-0190(80)90006-X","article-title":"Area-time optimal VLSI networks for parallel matrix multiplication","volume":"11","author":"Preparata","year":"1980","journal-title":"Inform. Process. Lett."},{"key":"10.1016\/0022-0000(81)90029-5_BIB7","first-page":"203","article-title":"The Design and Analysis of Computer Algorithms","author":"Aho","year":"1974"},{"key":"10.1016\/0022-0000(81)90029-5_BIB8","unstructured":"See [7, p. 242]."},{"key":"10.1016\/0022-0000(81)90029-5_BIB9","series-title":"Proc. Conf. Very Large Scale Integration: Architecture, Design, Fabrication","article-title":"Direct VLSI Implementation of Combinatorial Algorithms","author":"Guibas","year":"1979"}],"container-title":["Journal of Computer and System Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0022000081900295?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0022000081900295?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,16]],"date-time":"2019-02-16T13:29:54Z","timestamp":1550323794000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0022000081900295"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1981,4]]},"references-count":9,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1981,4]]}},"alternative-id":["0022000081900295"],"URL":"https:\/\/doi.org\/10.1016\/0022-0000(81)90029-5","relation":{},"ISSN":["0022-0000"],"issn-type":[{"type":"print","value":"0022-0000"}],"subject":[],"published":{"date-parts":[[1981,4]]}}}