{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,10]],"date-time":"2023-01-10T19:59:41Z","timestamp":1673380781515},"reference-count":17,"publisher":"Elsevier BV","issue":"4","license":[{"start":{"date-parts":[[1994,7,1]],"date-time":"1994-07-01T00:00:00Z","timestamp":773020800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computers & Graphics"],"published-print":{"date-parts":[[1994,7]]},"DOI":"10.1016\/0097-8493(94)90063-9","type":"journal-article","created":{"date-parts":[[2003,8,7]],"date-time":"2003-08-07T23:49:30Z","timestamp":1060300170000},"page":"507-516","source":"Crossref","is-referenced-by-count":9,"title":["LUT-based FPGA technology mapping under arbitrary net-delay models"],"prefix":"10.1016","volume":"18","author":[{"given":"Jason","family":"Cong","sequence":"first","affiliation":[]},{"given":"Yuzheng","family":"Ding","sequence":"additional","affiliation":[]},{"given":"Tong","family":"Gao","sequence":"additional","affiliation":[]},{"given":"Kuang-Chien","family":"Chen","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0097-8493(94)90063-9_BIB1","series-title":"The Programmable Gate Array Data Book","author":"Xilinx","year":"1992"},{"key":"10.1016\/0097-8493(94)90063-9_BIB2","series-title":"Proc. 28th ACM\/IEEE Design Automation Conf.","first-page":"187","article-title":"A CAD system for the design of field programmable gate arrays","author":"Hill","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB3","series-title":"Proc. 27th ACM\/IEEE Design Automation Conf.","first-page":"620","article-title":"Logic synthesis algorithms for programmable gate arrays","author":"Murgai","year":"1990"},{"key":"10.1016\/0097-8493(94)90063-9_BIB4","series-title":"Proc. IEEE Int'l Conf. on Computer-Aided Design","first-page":"564","article-title":"Improved logic synthesis algorithms for table look up architectures","author":"Murgai","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB5","series-title":"Proc. 28th ACM\/IEEE Design Automation Conf.","first-page":"613","article-title":"Chortle-crf: Fast technology mapping for lookup table-based FPGAs","author":"Francis","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB6","series-title":"Proc. 28th ACM\/IEEE Design Automation Conf.","first-page":"240","article-title":"Xmap: A technology mapper for table-lookup field-programmable gate arrays","author":"Karplus","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB7","series-title":"Proc. 28th ACM\/IEEE Design Automation Conf.","first-page":"248","article-title":"A heuristic method for FPGA technology mapping based on the edge visibility","author":"Woo","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB8","series-title":"ACM\/SIGDA Workshop on Field Programmable Gate Arrays","first-page":"83","article-title":"Technology mapping for table-look-up based field programmable gate arrays","author":"Sawkar","year":"1992"},{"key":"10.1016\/0097-8493(94)90063-9_BIB9","series-title":"Proc. IEEE Int'l Conf. on Computer-Aided Design","first-page":"572","article-title":"Performance directed synthesis for table look up programmable gate arrays","author":"Murgai","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB10","series-title":"MCNC Logic Synthesis Workshop","article-title":"Technology mapping for delay optimization of lookup table-based FPGAs","author":"Francis","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB11","series-title":"IEEE Design and Test of Computers","first-page":"7","article-title":"DAG-map: Graph-based FPGA technology mapping for delay optimization","author":"Chen","year":"1992"},{"key":"10.1016\/0097-8493(94)90063-9_BIB12","series-title":"Proc. IEEE Int'l Conf. on Computer-Aided Design","first-page":"48","article-title":"An optimal technology mapping algorithm of delay optimization in lookup-table based FPGA designs","author":"Cong","year":"1992"},{"key":"10.1016\/0097-8493(94)90063-9_BIB13","series-title":"First Int'l ACM\/SIGDA Workshop on Field Programmable Gate Arrays","first-page":"143","article-title":"Routable technology mapping for FPGAs","author":"Bhat","year":"1992"},{"key":"10.1016\/0097-8493(94)90063-9_BIB14","series-title":"Proc. IEEE International Conference on Computer Design","first-page":"86","article-title":"Routability-driven technology mapping for lookup table-based FPGAs","author":"Schlag","year":"1992"},{"key":"10.1016\/0097-8493(94)90063-9_BIB15","series-title":"Proc. 1st Int'l Workshop on Field Programmable Logic and Applications","article-title":"Empirical evaluation of multilevel logic minimization tools for a field programmable gate array technology","author":"Schlag","year":"1991"},{"key":"10.1016\/0097-8493(94)90063-9_BIB16","series-title":"Flows in Networks","author":"Ford","year":"1962"},{"key":"10.1016\/0097-8493(94)90063-9_BIB17","series-title":"Data Structures and Network Algorithms","author":"Tarjan","year":"1983"}],"container-title":["Computers & Graphics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0097849394900639?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0097849394900639?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T06:58:29Z","timestamp":1552633109000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0097849394900639"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,7]]},"references-count":17,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1994,7]]}},"alternative-id":["0097849394900639"],"URL":"https:\/\/doi.org\/10.1016\/0097-8493(94)90063-9","relation":{},"ISSN":["0097-8493"],"issn-type":[{"value":"0097-8493","type":"print"}],"subject":[],"published":{"date-parts":[[1994,7]]}}}