{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T00:20:40Z","timestamp":1649031640193},"reference-count":9,"publisher":"Elsevier BV","issue":"9","license":[{"start":{"date-parts":[[1982,11,1]],"date-time":"1982-11-01T00:00:00Z","timestamp":404956800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[1982,11]]},"DOI":"10.1016\/0141-9331(82)90492-6","type":"journal-article","created":{"date-parts":[[2003,3,15]],"date-time":"2003-03-15T01:34:01Z","timestamp":1047692041000},"page":"489-495","source":"Crossref","is-referenced-by-count":3,"title":["IEEE P896\u2014the Futurebus project"],"prefix":"10.1016","volume":"6","author":[{"given":"Paul","family":"Borrill","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0141-9331(82)90492-6_BIB1","volume":"Vols 1 and 2","author":"Catt","year":"1978"},{"key":"10.1016\/0141-9331(82)90492-6_BIB2","series-title":"Transmission Lines with Pulse Exitation","author":"Metzger","year":"1969"},{"key":"10.1016\/0141-9331(82)90492-6_BIB3","series-title":"Transmission Lines for Digital and Communication Networks","author":"Matick","year":"1969"},{"key":"10.1016\/0141-9331(82)90492-6_BIB4","series-title":"Fall Joint Comput. Conf.","first-page":"719","article-title":"A systematic approach to the design of digital bussing structures","author":"Thurber","year":"1972"},{"key":"10.1016\/0141-9331(82)90492-6_BIB5","series-title":"Proc. Euromicro","article-title":"Arbiters, priority access conflicts and the glitch problem","author":"Muehlemann","year":"1979"},{"key":"10.1016\/0141-9331(82)90492-6_BIB6","doi-asserted-by":"crossref","DOI":"10.1109\/T-C.1973.223730","article-title":"Anomalous behavior of synchroniser and arbiter circuits","author":"Chaney","year":"1973","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0141-9331(82)90492-6_BIB7","doi-asserted-by":"crossref","DOI":"10.1109\/TC.1981.6312173","article-title":"General theory of metastable operation","author":"Marino","year":"1981","journal-title":"IEEE Trans. Comput."},{"issue":"No 5","key":"10.1016\/0141-9331(82)90492-6_BIB8","first-page":"3786","article-title":"Fastbus status from a designers point of view","volume":"Vol NS-28","author":"Gustavson","year":"1981","journal-title":"IEEE Trans Nucl. Sci."},{"key":"10.1016\/0141-9331(82)90492-6_BIB9","article-title":"Versatile memory bus handles mixed memories compatibly","author":"Papenberg","year":"1980","journal-title":"Electron. Des."}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0141933182904926?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0141933182904926?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,25]],"date-time":"2019-03-25T03:56:29Z","timestamp":1553486189000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0141933182904926"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1982,11]]},"references-count":9,"journal-issue":{"issue":"9","published-print":{"date-parts":[[1982,11]]}},"alternative-id":["0141933182904926"],"URL":"https:\/\/doi.org\/10.1016\/0141-9331(82)90492-6","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[1982,11]]}}}