{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,5]],"date-time":"2024-07-05T19:12:32Z","timestamp":1720206752664},"reference-count":48,"publisher":"Elsevier BV","issue":"10","license":[{"start":{"date-parts":[[1992,1,1]],"date-time":"1992-01-01T00:00:00Z","timestamp":694224000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[1992,1]]},"DOI":"10.1016\/0141-9331(92)90081-4","type":"journal-article","created":{"date-parts":[[2003,3,15]],"date-time":"2003-03-15T06:33:26Z","timestamp":1047710006000},"page":"517-527","source":"Crossref","is-referenced-by-count":5,"title":["VLSI asynchronous systems: specification and synthesis"],"prefix":"10.1016","volume":"16","author":[{"given":"Ganesh","family":"Gopalakrishnan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Venkatesh","family":"Akella","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0141-9331(92)90081-4_BIB1","series-title":"High Level VLSI Synthesis","author":"Camposano","year":"1991"},{"key":"10.1016\/0141-9331(92)90081-4_BIB2","series-title":"High-Level Synthesis: Introduction to Chip and System Design","author":"Gajski","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB3","first-page":"301","article-title":"The high-level synthesis of digital systems","volume":"Vol 78","author":"McFarland","year":"1990"},{"key":"10.1016\/0141-9331(92)90081-4_BIB4","doi-asserted-by":"crossref","DOI":"10.1145\/63526.63532","article-title":"Micropipelines","author":"Sutherland","year":"1989","journal-title":"Comm. ACM"},{"key":"10.1016\/0141-9331(92)90081-4_BIB5","series-title":"An Introduction to VLSI Systems","author":"Mead","year":"1980"},{"key":"10.1016\/0141-9331(92)90081-4_BIB6","article-title":"Some recent asynchronous system design methodologies","author":"Gopalakrishnan","year":"1990"},{"key":"10.1016\/0141-9331(92)90081-4_BIB7","series-title":"Communicating Sequential Processes","author":"Hoare","year":"1985"},{"key":"10.1016\/0141-9331(92)90081-4_BIB8","series-title":"Communication and Concurrency","author":"Milner","year":"1989"},{"key":"10.1016\/0141-9331(92)90081-4_BIB9","series-title":"Trace Theory for Automatic Hierarchical Verification of Speed-independent Circuits","author":"Dill","year":"1989"},{"key":"10.1016\/0141-9331(92)90081-4_BIB10","series-title":"Translating Programs into Delay Insensitive Circuits","author":"Ebergen","year":"1989"},{"key":"10.1016\/0141-9331(92)90081-4_BIB11","article-title":"A correctness criterion for asynchronous circuit verification and optimization","author":"Gopalakrishnan","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB12","series-title":"International Workshop on Field Programmable Logic and Applications","article-title":"Compiling Occam into Field-Programmable Gate Arrays","author":"Page","year":"1991"},{"key":"10.1016\/0141-9331(92)90081-4_BIB13","series-title":"UT Year of Programming Institute on Concurrent Programming","article-title":"Programming in VLSI: From communicating processes to delay-insensitive circuits","author":"Martin","year":"1989"},{"key":"10.1016\/0141-9331(92)90081-4_BIB14","article-title":"Handshake circuits: an intermediary between communicating processes and VLSI","author":"van Berkel","year":"1992","journal-title":"PhD thesis"},{"key":"10.1016\/0141-9331(92)90081-4_BIB15","article-title":"Translating concurrent communicating programs into asynchronous circuits","author":"Brunvand","year":"1991"},{"key":"10.1016\/0141-9331(92)90081-4_BIB16","series-title":"International Conference on Computer Aided Design (ICCAD)","article-title":"Shilpa: A high-level synthesis system for self-timed circuits","author":"Akella","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB17","unstructured":"Stevens K \u2018Meat: The most excellent asynchronous tool\u2019 Software system developed by Ken Stevens of HP Labs (currently at the Department of Computer Science, University of Calgary)"},{"key":"10.1016\/0141-9331(92)90081-4_BIB18","series-title":"TAU '92: 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems","article-title":"Synthesis of hazard-free control circuits from asynchronous finite state machine specifications","author":"Chu","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB19","series-title":"Proceedings of the International Conference on Computer Design","article-title":"Practical asynchronous controller design","author":"Nowick","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB20","series-title":"(1992) 26th Hawaiian International Conference on System Sciences","article-title":"The post office experience","author":"Coates","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB21","series-title":"IEEE Spectrum","first-page":"26","article-title":"How DEC developed Alpha","year":"1992"},{"issue":"No 11","key":"10.1016\/0141-9331(92)90081-4_BIB22","doi-asserted-by":"crossref","first-page":"1185","DOI":"10.1109\/43.41504","article-title":"Automatic synthesis of asynchronous circuits from high-level specifications","volume":"Vol 8","author":"Messerchmitt","year":"1989","journal-title":"IEEE Trans. Comput.-Aided Des."},{"key":"10.1016\/0141-9331(92)90081-4_BIB23","unstructured":"Brunvand, F Personal Communication, CS, University of Utah (1992)"},{"issue":"No 11","key":"10.1016\/0141-9331(92)90081-4_BIB24","doi-asserted-by":"crossref","first-page":"1651","DOI":"10.1109\/4.98986","article-title":"A zero-overhead self-timed 160 ns 54 bit CMOS divider","volume":"Vol 26","author":"Williams","year":"1991","journal-title":"IEEE J. Sol. State Circ."},{"key":"10.1016\/0141-9331(92)90081-4_BIB25","article-title":"Self-timed integrated circuits for digital signal processing","author":"Jacobs","year":"1989"},{"issue":"No 4","key":"10.1016\/0141-9331(92)90081-4_BIB26","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1109\/T-C.1973.223730","article-title":"Anomalous behavior of synchronizer and arbiter circuits","volume":"Vol C-22","author":"Chaney","year":"1973","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0141-9331(92)90081-4_BIB27","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1007\/BF01660032","article-title":"A formal model for defining and classifying delay-insensitive circuits and systems","volume":"Vol 1","author":"Udding","year":"1986","journal-title":"Distrib. Comput."},{"key":"10.1016\/0141-9331(92)90081-4_BIB28","series-title":"Proceedings of the DCC Workshop","article-title":"The design of a delay-insensitive stack","author":"Udding","year":"1990"},{"key":"10.1016\/0141-9331(92)90081-4_BIB29","article-title":"An introduction to modal logic and its applications on the concurrency workbench","author":"Aldwinckle","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB30","series-title":"Advanced Research in VLSI: Proceedings of the 1992 Brown\/MIT Conference","article-title":"Compiling joy to silicon","author":"Weber","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB31","article-title":"Self timed is self diagnostic","author":"David","year":"1990"},{"key":"10.1016\/0141-9331(92)90081-4_BIB32","article-title":"Testing delay-insensitive circuits","author":"Hazewindus","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB33","series-title":"Panel discussion TAU '92: 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems","article-title":"Why do asynchronous systems matter?","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB34","article-title":"A3000: An asynchronous clone of the R3000 processor","author":"Wolf","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB35","series-title":"Proceedings of the Glasgow Workshop on Functional Programming","article-title":"A practical technique for designing asynchronous finite-state machines","author":"Peyton-Jones","year":"1989"},{"key":"10.1016\/0141-9331(92)90081-4_BIB36","series-title":"The Design of the Non-Synchronous RISC \u2018NSR\u2019","author":"Brunvand","year":"1992"},{"key":"10.1016\/0141-9331(92)90081-4_BIB37","article-title":"Advances in asynchronous circuit theory: Part i: Gate and unbounded intertial delay models; and part ii: Bounded intertial delay models, mos circuits, design techniques","author":"Brzozowski","year":"1991"},{"key":"10.1016\/0141-9331(92)90081-4_BIB38","article-title":"Standard asynchronous modules","author":"Sutherland","year":"1986"},{"key":"10.1016\/0141-9331(92)90081-4_BIB39","series-title":"International Workshop on Field Programmable Logic and Applications","article-title":"Implementing self-timed systems with FPGAs","author":"Brunvand","year":"1991"},{"key":"10.1016\/0141-9331(92)90081-4_BIB40","article-title":"On the delay-sensitivity of gate networks","author":"Brzozowski","year":"1990"},{"key":"10.1016\/0141-9331(92)90081-4_BIB41","article-title":"Globally-asynchronous locally-synchronous systems","author":"Chapiro","year":"1984"},{"key":"10.1016\/0141-9331(92)90081-4_BIB42","series-title":"Proceedings of the Caltech Conference on VLSI","first-page":"375","article-title":"Synchronization strategies","author":"Stucki","year":"1979"},{"issue":"No 9","key":"10.1016\/0141-9331(92)90081-4_BIB43","doi-asserted-by":"crossref","first-page":"1005","DOI":"10.1109\/12.2252","article-title":"Q-modules: internally clocked delay-insensitive modules","volume":"Vol 37","author":"Rosenberger","year":"1988","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0141-9331(92)90081-4_BIB44","article-title":"Constrained synthesis and optimization of digital integrated circuits from behavioral specifications","author":"Ku","year":"1991"},{"issue":"No 12","key":"10.1016\/0141-9331(92)90081-4_BIB45","doi-asserted-by":"crossref","first-page":"1133","DOI":"10.1109\/TC.1982.1675937","article-title":"Direct implementation of asynchronous control units","volume":"Vol 31","author":"Hollaar","year":"1982","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0141-9331(92)90081-4_BIB46","series-title":"Proceedings of IEEE International Conference on Computer Design (ICCD)","article-title":"Vlsi programming and silicon compilation: a novel approach from Phillips Research","author":"van Berkel","year":"1988"},{"key":"10.1016\/0141-9331(92)90081-4_BIB47","series-title":"Proc. 1988 IFIP WG 10.2 International Working Conference on The Fusion of Hardware Design and Verification","first-page":"97","article-title":"Synthesis of self-timed circuits by program transformation","author":"Burns","year":"1988"},{"issue":"No 8","key":"10.1016\/0141-9331(92)90081-4_BIB48","doi-asserted-by":"crossref","first-page":"666","DOI":"10.1145\/359576.359585","article-title":"Communicating sequential processes","volume":"Vol 21","author":"Hoare","year":"1978","journal-title":"Comm. ACM"}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0141933192900814?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0141933192900814?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,25]],"date-time":"2019-03-25T08:27:55Z","timestamp":1553502475000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0141933192900814"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1992,1]]},"references-count":48,"journal-issue":{"issue":"10","published-print":{"date-parts":[[1992,1]]}},"alternative-id":["0141933192900814"],"URL":"https:\/\/doi.org\/10.1016\/0141-9331(92)90081-4","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[1992,1]]}}}