{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T08:35:54Z","timestamp":1648542954250},"reference-count":41,"publisher":"Elsevier BV","issue":"4","license":[{"start":{"date-parts":[[1993,5,1]],"date-time":"1993-05-01T00:00:00Z","timestamp":736214400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[1993,5]]},"DOI":"10.1016\/0141-9331(93)90021-x","type":"journal-article","created":{"date-parts":[[2003,3,15]],"date-time":"2003-03-15T06:33:26Z","timestamp":1047710006000},"page":"232-242","source":"Crossref","is-referenced-by-count":0,"title":["Automated synthesis of asynchronous interface circuits"],"prefix":"10.1016","volume":"17","author":[{"given":"L","family":"Lavagno","sequence":"first","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]},{"given":"A","family":"Sangiovanni-Vincentelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocab":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0141-9331(93)90021-X_BIB1","series-title":"Introduction to VLSI Systems","author":"Seitz","year":"1981"},{"key":"10.1016\/0141-9331(93)90021-X_BIB2_1","doi-asserted-by":"crossref","first-page":"161","DOI":"10.1016\/0016-0032(54)90574-8","article-title":"The synthesis of sequential switching circuits","volume":"Vol 257","author":"Huffman","year":"1954","journal-title":"J. Franklin Inst."},{"key":"10.1016\/0141-9331(93)90021-X_BIB2_2","doi-asserted-by":"crossref","first-page":"275","DOI":"10.1016\/0016-0032(54)90618-3","article-title":"The synthesis of sequential switching circuits","volume":"Vol 257","author":"Huffman","year":"1954","journal-title":"J. Franklin Inst."},{"issue":"No 4","key":"10.1016\/0141-9331(93)90021-X_BIB3","doi-asserted-by":"crossref","first-page":"551","DOI":"10.1109\/PGEC.1966.264362","article-title":"Internal state assignments for asynchronous sequential machines","volume":"Vol EC-15","author":"Tracey","year":"1966","journal-title":"IEEE Trans. Electron. Comput."},{"key":"10.1016\/0141-9331(93)90021-X_BIB4","series-title":"Asynchronous Sequential Switching Circuits","author":"Unger","year":"1969"},{"key":"10.1016\/0141-9331(93)90021-X_BIB5","series-title":"Proceedings of the Fifth Annual IEEE Symposium on Logic in Computer Science","first-page":"414","article-title":"Model-checking for real-time systems","author":"Alur","year":"1990"},{"key":"10.1016\/0141-9331(93)90021-X_BIB6","series-title":"Annals of Computing Laboratory of Harvard University","first-page":"204","article-title":"A theory of asynchronous circuits","author":"Muller","year":"1959"},{"key":"10.1016\/0141-9331(93)90021-X_BIB7","volume":"Vol 2","author":"Miller","year":"1965"},{"issue":"No 12","key":"10.1016\/0141-9331(93)90021-X_BIB8","doi-asserted-by":"crossref","first-page":"1110","DOI":"10.1109\/T-C.1969.222594","article-title":"Design of asynchronous circuits assuming unbounded gate delays","volume":"Vol C-18","author":"Armstrong","year":"1969","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0141-9331(93)90021-X_BIB9","series-title":"Self-timed Control of Concurrent Processes","author":"Varshavsky","year":"1990"},{"key":"10.1016\/0141-9331(93)90021-X_BIB10","series-title":"Proceedings of the International Conference on Computer-Aided Design","article-title":"Synthesis of hazard-free asynchronous circuits from graphical specifications","author":"Moon","year":"1991"},{"key":"10.1016\/0141-9331(93)90021-X_BIB11","series-title":"ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems","article-title":"Gate-level synthesis of speed-independent asynchronous control circuits","author":"Beerel","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB12","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1007\/BF01660032","article-title":"A formal model for defining and classifying delay-insensitive circuits and systems","volume":"Vol 1","author":"Udding","year":"1986","journal-title":"Distrib. Comput."},{"key":"10.1016\/0141-9331(93)90021-X_BIB13","series-title":"Hawaii International Conf. on System Sciences","first-page":"55","article-title":"Speed independent asynchronous circuits","author":"Patil","year":"1971"},{"key":"10.1016\/0141-9331(93)90021-X_BIB14","series-title":"Advanced Research in VLSI Conference","article-title":"The limitations to delay-insensitivity in asynchronous circuits","author":"Martin","year":"1990"},{"key":"10.1016\/0141-9331(93)90021-X_BIB15","series-title":"Proceedings of the International Conference on Computer Design","article-title":"A synthesis method for selftimed VLSI circuits","author":"Burns","year":"1987"},{"key":"10.1016\/0141-9331(93)90021-X_BIB16","doi-asserted-by":"crossref","DOI":"10.1109\/12.2252","article-title":"Q-modules: Internally clocked delay-insensitive modules","volume":"Vol 37","author":"Rosenberger","year":"1988","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0141-9331(93)90021-X_BIB17","series-title":"Translating Programs into Delay-Insensitive Circuits","author":"Ebergen","year":"1989"},{"key":"10.1016\/0141-9331(93)90021-X_BIB18","series-title":"Proceedings of the International Conference on Computer-Aided Design","first-page":"262","article-title":"Translating concurrent programs into delay-insensitive circuits","author":"Brunvand","year":"1989"},{"key":"10.1016\/0141-9331(93)90021-X_BIB19","series-title":"CONCUR '90, Theories of Concurrency: Unification and Extension","first-page":"342","article-title":"Delay-insensitive circuits: An algebraic approach to their design","volume":"Vol 458","author":"Josephs","year":"1990"},{"key":"10.1016\/0141-9331(93)90021-X_BIB20","doi-asserted-by":"crossref","DOI":"10.1145\/63526.63532","article-title":"Micropipelines","author":"Sutherland","year":"1989","journal-title":"Comm. ACM"},{"key":"10.1016\/0141-9331(93)90021-X_BIB21","series-title":"International Workshop on Timed Petri Nets","article-title":"Signal graphs: from self-timed to timed ones","author":"Rosenblum","year":"1985"},{"key":"10.1016\/0141-9331(93)90021-X_BIB22","series-title":"Proceedings of the International Conference on Computer Design","first-page":"565","article-title":"Synthesis of self-timed control circuits from graphs: an example","author":"Chu","year":"1986"},{"key":"10.1016\/0141-9331(93)90021-X_BIB23","article-title":"Synthesis of self-timed VLSI circuits from graph-theoretic specifications","author":"Chu","year":"1987"},{"key":"10.1016\/0141-9331(93)90021-X_BIB24","series-title":"ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems","article-title":"On self-timed behavior verification","author":"Kishinevsky","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB25","article-title":"Asynchronous design for digital signal processing architectures","author":"Meng","year":"1988"},{"key":"10.1016\/0141-9331(93)90021-X_BIB26","series-title":"Proceedings of the International Conference on Computer Design","article-title":"Sequential circuit design using synthesis and optimization","author":"Sentovich","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB27","article-title":"SIS: A system for sequential circuit synthesis","author":"Sentovich","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB28","series-title":"Advanced Research in VLSI Conference","article-title":"Synthesis of verifiably hazard-free asynchronous control circuits","author":"Lavagno","year":"1991"},{"key":"10.1016\/0141-9331(93)90021-X_BIB29","series-title":"Proceedings of the Design Automation Conference","article-title":"Algorithms for synthesis of hazard-free asynchronous circuits","author":"Lavagno","year":"1991"},{"key":"10.1016\/0141-9331(93)90021-X_BIB30","series-title":"Proceedings of the International Conference on Computer-Aided Design","article-title":"Synthesis for testability techniques for asynchronous circuits","author":"Lavagno","year":"1991"},{"key":"10.1016\/0141-9331(93)90021-X_BIB31","series-title":"Proceedings of the Design Automation Conference","article-title":"Solving the state assignment problem for signal transition graphs","author":"Lavagno","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB32","series-title":"Proceedings of the International Conference on Computer Design","article-title":"Linear programming for optimal hazard removal in asynchronous circuits","author":"Lavagno","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB33","article-title":"A new interface specification methodology and its application to transducer synthesis","author":"Borriello","year":"1988"},{"key":"10.1016\/0141-9331(93)90021-X_BIB34","article-title":"Kommunikation mit Automaten","author":"Petri","year":"1962"},{"key":"10.1016\/0141-9331(93)90021-X_BIB35","volume":"Vol 9","author":"Peterson","year":"1977"},{"key":"10.1016\/0141-9331(93)90021-X_BIB36","series-title":"Proc. IEEE","first-page":"541","article-title":"Petri nets: Properties, analysis and applications","author":"Murata","year":"1989"},{"key":"10.1016\/0141-9331(93)90021-X_BIB37","series-title":"Sixth International Conference on Distributed Computing Systems","article-title":"The post office \u2014 communication support for distributed ensemble architectures","author":"Stevens","year":"1986"},{"key":"10.1016\/0141-9331(93)90021-X_BIB38","series-title":"ACM Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems","article-title":"Synthesis of hazard-free control circuits form asynchronous finite state machine specifications","author":"Chu","year":"1992"},{"key":"10.1016\/0141-9331(93)90021-X_BIB39","series-title":"Proceedings of the International Conference on Computer-Aided Design","article-title":"Automatic synthesis of locally-clocked asynchronous state machines","author":"Nowick","year":"1991"},{"issue":"No 15","key":"10.1016\/0141-9331(93)90021-X_BIB40","first-page":"55","article-title":"Build a VMEbus interface with PAL devices","volume":"Vol 37","author":"Shankar","year":"1989","journal-title":"Electron. Des."}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:014193319390021X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:014193319390021X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,25]],"date-time":"2019-03-25T08:29:01Z","timestamp":1553502541000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/014193319390021X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,5]]},"references-count":41,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1993,5]]}},"alternative-id":["014193319390021X"],"URL":"https:\/\/doi.org\/10.1016\/0141-9331(93)90021-x","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[1993,5]]}}}