{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:40:23Z","timestamp":1773193223868,"version":"3.50.1"},"reference-count":13,"publisher":"Elsevier BV","issue":"1","license":[{"start":{"date-parts":[[1995,1,1]],"date-time":"1995-01-01T00:00:00Z","timestamp":788918400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[1995,1]]},"DOI":"10.1016\/0141-9331(95)93086-x","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T22:50:06Z","timestamp":1027637406000},"page":"35-42","source":"Crossref","is-referenced-by-count":24,"title":["Fast context switches: compiler and architectural support for preemptive scheduling"],"prefix":"10.1016","volume":"19","author":[{"given":"Jeffrey S.","family":"Snyder","sequence":"first","affiliation":[]},{"given":"David B.","family":"Whalley","sequence":"additional","affiliation":[]},{"given":"Theodore P.","family":"Baker","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0141-9331(95)93086-X_BIB1","series-title":"Real-Time Systems Design","author":"Levi","year":"1990"},{"key":"10.1016\/0141-9331(95)93086-X_BIB2","series-title":"Proc. 4th International Conference on Architectural Support for Programming Languages and Operating Systems","first-page":"75","article-title":"The effect of context switches on cache performance","author":"Mogul","year":"1991"},{"issue":"No 4","key":"10.1016\/0141-9331(95)93086-X_BIB3","doi-asserted-by":"crossref","first-page":"393","DOI":"10.1145\/48012.48037","article-title":"Cache performance of operating system and multiprogram workloads","volume":"Vol 6","author":"Agarwal","year":"1988","journal-title":"ACM Trans. Comput. Syst."},{"issue":"No 3","key":"10.1016\/0141-9331(95)93086-X_BIB4","doi-asserted-by":"crossref","first-page":"320","DOI":"10.1145\/115953.115984","article-title":"Flexible register management for sequential programs","volume":"Vol 19","author":"Quammen","year":"1991","journal-title":"18th Annual International Symposium on Computer Architecture"},{"key":"10.1016\/0141-9331(95)93086-X_BIB5","series-title":"Proc. 4th International Conference on Architectural Support for Programming Languages and Operating Systems","first-page":"75","article-title":"Exploiting of context switches on cache performance","author":"Miller","year":"1991"},{"key":"10.1016\/0141-9331(95)93086-X_BIB6","series-title":"Centralized and Distributed Operating Systems","author":"Nutt","year":"1992"},{"key":"10.1016\/0141-9331(95)93086-X_BIB7","series-title":"Proc. 4th International Conference on Architectural Support for Programming Languages and Operating Systems","first-page":"108","article-title":"The interaction of architecture and operating system design","author":"Anderson","year":"1991"},{"key":"10.1016\/0141-9331(95)93086-X_BIB8","series-title":"Proc. SIGPLAN '88 Symposium on Programming Language Design and Implementation","first-page":"329","article-title":"A portable global optimizer and linker","author":"Benitez","year":"1988"},{"issue":"No 9","key":"10.1016\/0141-9331(95)93086-X_BIB9","doi-asserted-by":"crossref","first-page":"459","DOI":"10.1016\/0141-9331(91)90002-W","article-title":"A design environment for addressing architecture and compiler interactions","volume":"Vol 15","author":"Davidson","year":"1991","journal-title":"Microprocessors Microsyst."},{"issue":"No 2","key":"10.1016\/0141-9331(95)93086-X_BIB10","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1002\/spe.4380210204","article-title":"Methods for saving and restoring register values across function calls","volume":"Vol 21","author":"Davidson","year":"1991","journal-title":"Softw. Pract. Exper."},{"key":"10.1016\/0141-9331(95)93086-X_BIB11","article-title":"Fast context switches","author":"Snyder","year":"1992"},{"issue":"No 6","key":"10.1016\/0141-9331(95)93086-X_BIB12","doi-asserted-by":"crossref","first-page":"357","DOI":"10.1016\/0141-9331(90)90108-8","article-title":"RISC system\/6000 power architecture","volume":"Vol 14","author":"Groves","year":"1990","journal-title":"Microprocessors Microsyst."},{"issue":"No 6","key":"10.1016\/0141-9331(95)93086-X_BIB13","doi-asserted-by":"crossref","first-page":"417","DOI":"10.1016\/0141-9331(90)90114-B","article-title":"SPARC: architecture to implementations","volume":"Vol 14","year":"1990","journal-title":"Microprocessors Microsyst."}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:014193319593086X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:014193319593086X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,18]],"date-time":"2019-04-18T19:51:00Z","timestamp":1555617060000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/014193319593086X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":13,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["014193319593086X"],"URL":"https:\/\/doi.org\/10.1016\/0141-9331(95)93086-x","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}