{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T16:24:56Z","timestamp":1648830296525},"reference-count":9,"publisher":"Elsevier BV","issue":"3-4","license":[{"start":{"date-parts":[[1983,10,1]],"date-time":"1983-10-01T00:00:00Z","timestamp":433814400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1983,10]]},"DOI":"10.1016\/0165-6074(83)90091-1","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T04:56:11Z","timestamp":1060318571000},"page":"159-165","source":"Crossref","is-referenced-by-count":0,"title":["Using the iAPX-432 system as a support for chill parallel constructs"],"prefix":"10.1016","volume":"12","author":[{"given":"Antonio","family":"Corradi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio","family":"Natali","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"n.9","key":"10.1016\/0165-6074(83)90091-1_BIB1","doi-asserted-by":"crossref","DOI":"10.1109\/MC.1982.1654133","article-title":"A VLSI RISC","volume":"vol. 15","author":"Patterson","year":"1982","journal-title":"Computer"},{"key":"10.1016\/0165-6074(83)90091-1_BIB2","unstructured":"Intel, iAPX 432 Architecture Reference Manual, Intel order n.171860."},{"key":"10.1016\/0165-6074(83)90091-1_BIB3","series-title":"A Programmer's View of the Intel 432 System","author":"Organick","year":"1982"},{"key":"10.1016\/0165-6074(83)90091-1_BIB4","unstructured":"Intel, Introduction to the iAPX 432 Architecture, Intel order n.171821."},{"issue":"n.6","key":"10.1016\/0165-6074(83)90091-1_BIB5","doi-asserted-by":"crossref","DOI":"10.1145\/355616.364017","article-title":"HYDRA: the Kernel of a Multiprocessor Operating System","volume":"vol. 17","author":"Wulf","year":"1974","journal-title":"CACM"},{"key":"10.1016\/0165-6074(83)90091-1_BIB6","series-title":"HYDRA\/C.mmp: an Experimental Computer System","author":"Wulf","year":"1981"},{"key":"10.1016\/0165-6074(83)90091-1_BIB7","series-title":"CCITT Period","article-title":"CHILL Language Definition","author":"CCITT","year":"1980"},{"issue":"n.1","key":"10.1016\/0165-6074(83)90091-1_BIB8","doi-asserted-by":"crossref","DOI":"10.1145\/357353.357358","article-title":"Interprocess Communication and Processor Dispatching on the Intel 432","volume":"vol. 1","author":"Cox","year":"1983","journal-title":"ACM Transaction on Computer Systems"},{"key":"10.1016\/0165-6074(83)90091-1_BIB9","author":"Department of Defense","year":"1980"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607483900911?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607483900911?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T02:50:47Z","timestamp":1552618247000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607483900911"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1983,10]]},"references-count":9,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[1983,10]]}},"alternative-id":["0165607483900911"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(83)90091-1","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1983,10]]}}}