{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T09:05:44Z","timestamp":1648976744664},"reference-count":6,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1984,3,1]],"date-time":"1984-03-01T00:00:00Z","timestamp":446947200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1984,3]]},"DOI":"10.1016\/0165-6074(84)90027-9","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T04:56:11Z","timestamp":1060318571000},"page":"153-170","source":"Crossref","is-referenced-by-count":0,"title":["Hierarchical emulation of well-coded programs through the use of streams of instructions buffered in on-chip associative memories and distributed control"],"prefix":"10.1016","volume":"13","author":[{"given":"Dany","family":"Suk","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gunnar","family":"Carlstedt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"No. 3","key":"10.1016\/0165-6074(84)90027-9_BIB1","doi-asserted-by":"crossref","first-page":"237","DOI":"10.1145\/359361.359454","article-title":"Implications of structured programming for machine architecture","volume":"Vol. 21","author":"Tanenbaum","year":"1978","journal-title":"Communications, Association for Computing Machinery"},{"key":"10.1016\/0165-6074(84)90027-9_BIB2","first-page":"579","article-title":"Burroughs B1700 Memory Utilization","volume":"Vol. 41","author":"Wilner","year":"1972"},{"key":"10.1016\/0165-6074(84)90027-9_BIB3","first-page":"489","article-title":"Design of Burroughs B1700","volume":"Vol. 41","author":"Wilner","year":"1972"},{"key":"10.1016\/0165-6074(84)90027-9_BIB4","series-title":"Proceedings, IRE 40","first-page":"1098","article-title":"Method for construction of minimum redundancy codes","author":"Huffman","year":"1952"},{"key":"10.1016\/0165-6074(84)90027-9_BIB5","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/MC.1982.1654133","article-title":"A VLSI RISC","author":"Patterson","year":"1982","journal-title":"Computer"},{"key":"10.1016\/0165-6074(84)90027-9_BIB6","article-title":"Hierarchical Emulation of Well-Coded Programs through the Use of Streams of Instructions Buffered in On-Chip Association Memories and Distributed Control","author":"Suk","year":"1983"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607484900279?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607484900279?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T02:51:12Z","timestamp":1552618272000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607484900279"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1984,3]]},"references-count":6,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1984,3]]}},"alternative-id":["0165607484900279"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(84)90027-9","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1984,3]]}}}