{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T22:55:12Z","timestamp":1648853712860},"reference-count":8,"publisher":"Elsevier BV","issue":"2-3","license":[{"start":{"date-parts":[[1985,9,1]],"date-time":"1985-09-01T00:00:00Z","timestamp":494380800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1985,9]]},"DOI":"10.1016\/0165-6074(85)90040-7","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T00:56:11Z","timestamp":1060304171000},"page":"61-65","source":"Crossref","is-referenced-by-count":0,"title":["LAPLACE: Another second generation PLA design tool"],"prefix":"10.1016","volume":"16","author":[{"given":"Alessandro","family":"Cagnola","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Corti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giorgio","family":"Vignati","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(85)90040-7_BIB1","series-title":"Introduction to VLSI systems","author":"Mead","year":"1980"},{"key":"10.1016\/0165-6074(85)90040-7_BIB2","article-title":"An interactive PLA Generator as an Archetype for a New VLSI Design Methodology","author":"Glasser","year":"1980","journal-title":"MIT Vlsi Memo 80-25"},{"key":"10.1016\/0165-6074(85)90040-7_BIB3","series-title":"21st Design Automation Conference","article-title":"A VLSI FSM Design System","author":"Meyer","year":"1984"},{"key":"10.1016\/0165-6074(85)90040-7_BIB4","series-title":"20th Design Automation Conference","article-title":"APSS: an automatic PLA synthesis system","author":"Stebnisky","year":"1983"},{"key":"10.1016\/0165-6074(85)90040-7_BIB5","series-title":"Caltech Conference on VLSI","article-title":"Signal Delay in RC Tree Networks","author":"Rubinstein","year":"1981"},{"key":"10.1016\/0165-6074(85)90040-7_BIB6","series-title":"Proc. of 20th Design Automation Conference","article-title":"Path delay analysis for hierarchical building block layout system","author":"Tamura","year":"1983"},{"issue":"No. 4","key":"10.1016\/0165-6074(85)90040-7_BIB7","article-title":"Signal delay in general RC networks","author":"Lin","year":"1984","journal-title":"IEEE Trans. on CAD"},{"key":"10.1016\/0165-6074(85)90040-7_BIB8","series-title":"Technical Report No. SEL83-003","article-title":"Timing models for MOS circuits","author":"Horowitz","year":"1983"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607485900407?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607485900407?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,14]],"date-time":"2019-03-14T22:52:42Z","timestamp":1552603962000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607485900407"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1985,9]]},"references-count":8,"journal-issue":{"issue":"2-3","published-print":{"date-parts":[[1985,9]]}},"alternative-id":["0165607485900407"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(85)90040-7","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1985,9]]}}}