{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T07:50:35Z","timestamp":1649145035377},"reference-count":19,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1987,8,1]],"date-time":"1987-08-01T00:00:00Z","timestamp":554774400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1987,8]]},"DOI":"10.1016\/0165-6074(87)90019-6","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"65-71","source":"Crossref","is-referenced-by-count":6,"title":["A flexible architecture for image processing"],"prefix":"10.1016","volume":"21","author":[{"given":"R.W","family":"Hartenstein","sequence":"first","affiliation":[]},{"given":"A","family":"Hirschbiel","sequence":"additional","affiliation":[]},{"given":"M","family":"Weber","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(87)90019-6_BIB1","article-title":"VLSI-Algorithmen: Innovative Schaltungstechnik statt Software \u2013 Shuffle Sort","author":"Bastian","year":"1985","journal-title":"VDI-Berichte Nr. 550"},{"key":"10.1016\/0165-6074(87)90019-6_BIB2","doi-asserted-by":"crossref","DOI":"10.1109\/MDT.1984.5005647","article-title":"A Survey of Hardware Accelerators used in Computer-Aided Design","author":"Blank","year":"1984","journal-title":"IEEE Design and Test of Computers"},{"issue":"Issue 4","key":"10.1016\/0165-6074(87)90019-6_BIB3","article-title":"A Hardware Router","volume":"Vol. 4","author":"Breuer","year":"1981","journal-title":"Journal of Digital Systems"},{"key":"10.1016\/0165-6074(87)90019-6_BIB4","doi-asserted-by":"crossref","DOI":"10.1109\/MC.1980.1653338","article-title":"The Design of Special-Purpose VLSI Chips","author":"Foster","year":"1980","journal-title":"Computer"},{"key":"10.1016\/0165-6074(87)90019-6_BIB5","series-title":"Functional Extraction from Personality Matrices of MOL (Matrix Oriented Logic) Circuits","author":"Gebhardt","year":"1986"},{"key":"10.1016\/0165-6074(87)90019-6_BIB6","series-title":"PISA Maschine, Eine spezielle Hardware f\u00fcr pixel orientierte Bildverarbeitung","author":"Hirschbiel","year":"1985"},{"key":"10.1016\/0165-6074(87)90019-6_BIB7","series-title":"ICCAD - 84, Digest of Technical Papers","article-title":"PISA, A CAD Package And Special Hardware For Pixel-Oritented Layout Analysis","author":"Hartenstein","year":"1984"},{"issue":"No. 4","key":"10.1016\/0165-6074(87)90019-6_BIB8","doi-asserted-by":"crossref","DOI":"10.1109\/JSSC.1980.1051462","article-title":"A Dense Gate Matrix Layout Method for MOS VLSI","volume":"Vol. SC-15","author":"Lopez","year":"1980","journal-title":"IEEE Journal of solid-state circuit"},{"key":"10.1016\/0165-6074(87)90019-6_BIB9","series-title":"Caltech Conference on VLSI","article-title":"Let's Design Algorithms for VLSI","author":"Kung","year":"1979"},{"key":"10.1016\/0165-6074(87)90019-6_BIB10","series-title":"Why Systolic Architectures?","author":"Kung","year":"1982"},{"key":"10.1016\/0165-6074(87)90019-6_BIB11","first-page":"346","article-title":"An Algorithm For Path Connections And Its Applications","volume":"vol EC-10","author":"Lee","year":"1961"},{"key":"10.1016\/0165-6074(87)90019-6_BIB12","series-title":"Introduction to VLSI Systems","author":"Mead","year":"1980"},{"key":"10.1016\/0165-6074(87)90019-6_BIB13","series-title":"CAD-Entwurfskontrolle in der Mikroelektronik","author":"Nebel","year":"1985"},{"key":"10.1016\/0165-6074(87)90019-6_BIB14","series-title":"Multicomputers and Image Processing","author":"Preston","year":"1982"},{"key":"10.1016\/0165-6074(87)90019-6_BIB15","series-title":"Algorithmically Specialized Parallel Computers","author":"Snyder","year":"1985"},{"key":"10.1016\/0165-6074(87)90019-6_BIB16","series-title":"Real\/Time Parallel Computers","first-page":"347","article-title":"Parallel architectures for image processing","author":"Sternberg","year":"1981"},{"key":"10.1016\/0165-6074(87)90019-6_BIB17","series-title":"Implementing des Lee-Algorithms auf MOM","author":"Velten","year":"1987"},{"issue":"No. 4","key":"10.1016\/0165-6074(87)90019-6_BIB18","doi-asserted-by":"crossref","DOI":"10.1109\/JSSC.1967.1049816","article-title":"Large Scale Integration of MOS Complex Logic: A Layout Method","volume":"Vol. SC-2","author":"Weinberger","year":"1967","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/0165-6074(87)90019-6_BIB19","author":"Young","year":"1986"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607487900196?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607487900196?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,3,25]],"date-time":"2020-03-25T09:56:12Z","timestamp":1585130172000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607487900196"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,8]]},"references-count":19,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1987,8]]}},"alternative-id":["0165607487900196"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(87)90019-6","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1987,8]]}}}