{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T23:23:52Z","timestamp":1648855432912},"reference-count":17,"publisher":"Elsevier BV","issue":"1","license":[{"start":{"date-parts":[[1987,1,1]],"date-time":"1987-01-01T00:00:00Z","timestamp":536457600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1987,1]]},"DOI":"10.1016\/0165-6074(87)90229-8","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T04:56:11Z","timestamp":1060318571000},"page":"5-17","source":"Crossref","is-referenced-by-count":0,"title":["Evaluation of a multiprocessor structure for image processing"],"prefix":"10.1016","volume":"19","author":[{"given":"Alberto","family":"Giordano","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fausto","family":"Giunchiglia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Massimo","family":"Maresca","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tullio","family":"Vernazza","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(87)90229-8_BIB1","unstructured":"MULTIBUS Specification Manual, Intel."},{"key":"10.1016\/0165-6074(87)90229-8_BIB2","unstructured":"LSI-11, Digital Equipment Corporation, Maynard, Massachussetts."},{"key":"10.1016\/0165-6074(87)90229-8_BIB3","unstructured":"VAX 11\/780 Hardware Handbook, Digital Equipment Corporation, Maynard, Massachussetts."},{"key":"10.1016\/0165-6074(87)90229-8_BIB4","series-title":"Proc. 6th ACM Symposium on Computer Architectures","article-title":"Processor\u2014Memory interconnection for multiprocessors","author":"Patel","year":"1979"},{"key":"10.1016\/0165-6074(87)90229-8_BIB5","series-title":"Why Systolic Architectures?","author":"Kung","year":"1980"},{"issue":"Nr.8","key":"10.1016\/0165-6074(87)90229-8_BIB6","article-title":"N-Channel asynchronous arbiter resolve resource allocation conflicts","volume":"Vol. 19","author":"Petriu","year":"1980","journal-title":"Computer Design"},{"key":"10.1016\/0165-6074(87)90229-8_BIB7","series-title":"Proc. AICA","article-title":"Multimicroprocessor system topologies and connection techniques","author":"Delcorso","year":"1980"},{"key":"10.1016\/0165-6074(87)90229-8_BIB8","series-title":"Proc. Int. Conf. on Cybernetics and Society","article-title":"Optimizing multiprocessor architectures by simulation","author":"Beauchamp","year":"1980"},{"key":"10.1016\/0165-6074(87)90229-8_BIB9","series-title":"Proc. AICA","article-title":"Una struttura a bus multipli orientata alla elaborazione di immagini","author":"Marino","year":"1980"},{"key":"10.1016\/0165-6074(87)90229-8_BIB10","year":"1981","journal-title":"VME Bus Specification Manual"},{"key":"10.1016\/0165-6074(87)90229-8_BIB11","series-title":"Architectural and software issues in the design and application of peripheral array processors","author":"Karplus","year":"1981"},{"issue":"Nr. 30","key":"10.1016\/0165-6074(87)90229-8_BIB12","article-title":"Performance of processor memory interconnections for multiprocessors","volume":"Vol. C","author":"Patel","year":"1981","journal-title":"IEE Trans. on Computers"},{"key":"10.1016\/0165-6074(87)90229-8_BIB13","series-title":"Cellular Logic Computers for pattern recognition","author":"Preston","year":"1983"},{"issue":"Nr. 4","key":"10.1016\/0165-6074(87)90229-8_BIB14","article-title":"Data format and bus compatibility in Multiprocessors","volume":"Vol. 3","author":"Kirrmann","year":"1983","journal-title":"IEEE Micro"},{"key":"10.1016\/0165-6074(87)90229-8_BIB15","series-title":"Proc. BIAS","article-title":"Realizzazione di un arbitro distribuito per un bus veloce","author":"Antognetti","year":"1983"},{"issue":"Nr.6","key":"10.1016\/0165-6074(87)90229-8_BIB16","article-title":"Multiprocessor bus is ready to meet 32 Bit Applications of Future","volume":"Vol.57","author":"Beaston","year":"1983","journal-title":"Electronics"},{"issue":"Nr.4","key":"10.1016\/0165-6074(87)90229-8_BIB17","article-title":"Arbitration and Control Acquisition in the Proposed IEEE 896 Futurebus","volume":"Vol.4","author":"Taub","year":"1984","journal-title":"IEEE Micro"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607487902298?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607487902298?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T02:54:58Z","timestamp":1552618498000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607487902298"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,1]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1987,1]]}},"alternative-id":["0165607487902298"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(87)90229-8","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1987,1]]}}}