{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,4,26]],"date-time":"2023-04-26T22:10:04Z","timestamp":1682547004047},"reference-count":36,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1988,8,1]],"date-time":"1988-08-01T00:00:00Z","timestamp":586396800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1988,8]]},"DOI":"10.1016\/0165-6074(88)90057-9","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"219-226","source":"Crossref","is-referenced-by-count":1,"title":["A language environment for asic design"],"prefix":"10.1016","volume":"24","author":[{"given":"Raivo","family":"Raud","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(88)90057-9_BIB1","volume":"151","author":"Piloty","year":"1983"},{"key":"10.1016\/0165-6074(88)90057-9_BIB2","series-title":"Theory and Design of Digital Machine","author":"Bartee","year":"1962"},{"key":"10.1016\/0165-6074(88)90057-9_BIB3","series-title":"Abtoko\u0433-m, \u043fok\u043f. 5-\u043d me\u0448by\u044d.koh\u03b8. \u043fo \u03b8\u043d\u044d-mat mo\u043fe\u044f\u043dp","author":"\u041fo\u043b\u042f\u043ao\u0431","year":"1968"},{"key":"10.1016\/0165-6074(88)90057-9_BIB4","series-title":"Proc. 5th CHDL's Applications","first-page":"79","article-title":"Modlan - a language for Multilevel Description and Modelling in Digital Systems","author":"Pavlac","year":"1981"},{"key":"10.1016\/0165-6074(88)90057-9_BIB5","doi-asserted-by":"crossref","first-page":"567","DOI":"10.1016\/0165-6074(86)90093-1","article-title":"A Language for Behavior, Structure & Geometry","author":"Carlstedt","year":"1986","journal-title":"Microprocessing & Microcomputing"},{"key":"10.1016\/0165-6074(88)90057-9_BIB6","doi-asserted-by":"crossref","first-page":"94","DOI":"10.1109\/MC.1985.1662802","article-title":"VHSIC Hardware Description Language","author":"Shahdad","year":"1985","journal-title":"Computer #2"},{"key":"10.1016\/0165-6074(88)90057-9_BIB7","series-title":"B C6. Texh\u043dka; \u044dkohom\u043dka, \u043dh\u03b8opmat\u043dka, cep. abtomat\u043d\u044d, \u043fpoektnp","first-page":"53","article-title":"\u03b8Opma - \u043a\u044d\u044bk texh\u043d\u0447eckto\u03b3 \u043d \u03b8yhk\u043d\u043dohabhoro \u043fpoekt\u043dpoba\u043d\u043a \u044dbm","author":"\u041feb\u043dh","year":"1986"},{"key":"10.1016\/0165-6074(88)90057-9_BIB8","doi-asserted-by":"crossref","first-page":"81","DOI":"10.1109\/MC.1985.1662801","article-title":"The Conlan Project: Concepts, Implementations and Applications","author":"Piloty","year":"1985","journal-title":"Computer #2"},{"key":"10.1016\/0165-6074(88)90057-9_BIB9","series-title":"Proc. 4th Symp. CHDL's","first-page":"144","article-title":"ADLIB: A Modular Strongly Typed Computer Design Language","author":"Hill","year":"1979"},{"key":"10.1016\/0165-6074(88)90057-9_BIB10","first-page":"27","article-title":"Introducing AHPL","author":"Hill","year":"1974","journal-title":"Computer #2"},{"key":"10.1016\/0165-6074(88)90057-9_BIB11","series-title":"APL\u2217DS - HDL for Design and Simulation","first-page":"45","year":"1975"},{"key":"10.1016\/0165-6074(88)90057-9_BIB12","doi-asserted-by":"crossref","first-page":"637","DOI":"10.1016\/0165-6074(86)90102-X","article-title":"Semantics of Hardware Specification Language","author":"Larson","year":"1986","journal-title":"Microprocessing & Microcomputing"},{"key":"10.1016\/0165-6074(88)90057-9_BIB13","series-title":"Proc. Comp. Appl. in Progr. & Engr.","first-page":"284","article-title":"Circuits and Systems Computer Aided Design and Engineering CASCADE","author":"Mermet","year":"1983"},{"key":"10.1016\/0165-6074(88)90057-9_BIB14","series-title":"Proc. IFIP Congress","first-page":"314","article-title":"Cassandre adn the Computer Aided Logical Systems Design","author":"Bago","year":"1971"},{"key":"10.1016\/0165-6074(88)90057-9_BIB15","series-title":"PRoc. CHDL's Applications","first-page":"143","article-title":"LASCAR - A Language of Computer Architecture","author":"Borrione","year":"1975"},{"key":"10.1016\/0165-6074(88)90057-9_BIB16","series-title":"Introduction to Computer Organization","author":"Chu","year":"1970"},{"key":"10.1016\/0165-6074(88)90057-9_BIB17","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1016\/0165-6074(86)90022-0","article-title":"Adapting TPDL\u2217 to Concurrent Simulatin Environments","author":"Cabodi","year":"1986","journal-title":"Microprocessing \u2217 Microcomputing"},{"key":"10.1016\/0165-6074(88)90057-9_BIB18","doi-asserted-by":"crossref","first-page":"850","DOI":"10.1109\/TC.1968.229145","article-title":"A Digital System Design Language (DDL)","author":"Dulley","year":"1968","journal-title":"IEEE Computer C-17 #9"},{"key":"10.1016\/0165-6074(88)90057-9_BIB19","doi-asserted-by":"crossref","first-page":"631","DOI":"10.1016\/0165-6074(86)90101-8","article-title":"The dependency notation as a graphical description language for logic design and silicon compilation","author":"Kivela","year":"1986","journal-title":"Microprocessing & Microcomputing"},{"key":"10.1016\/0165-6074(88)90057-9_BIB20","article-title":"Descriptive Techniques for Digital Hardware Description","author":"Tracey","year":"1980"},{"key":"10.1016\/0165-6074(88)90057-9_BIB21","series-title":"Computer Structures: Readings and Examples","author":"Bell","year":"1971"},{"key":"10.1016\/0165-6074(88)90057-9_BIB22","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/TC.1981.6312154","article-title":"Instruction set processor specification (ISPS): The notation and its application","author":"Barbacci","year":"1981","journal-title":"IEEE Computer C-30 #1"},{"issue":"#8","key":"10.1016\/0165-6074(88)90057-9_BIB23","doi-asserted-by":"crossref","first-page":"439","DOI":"10.1109\/PGEC.1964.263846","article-title":"A Formal Language for Describing Machine Logic","volume":"Ec-13","author":"Shlaepp","year":"1964","journal-title":"Timing and Sequencing (LOTIS), IEEE Electron. Comput."},{"key":"10.1016\/0165-6074(88)90057-9_BIB24","series-title":"IEEE 4th Conf. Inf. Techn.","first-page":"376","article-title":"PASS: A Simulator System for Parallel Architectures","author":"Webb","year":"1984"},{"issue":"#3","key":"10.1016\/0165-6074(88)90057-9_BIB25","first-page":"137","article-title":"Design Verification at the Register Transfer Level","volume":"C-24","author":"Hoehne","year":"1975","journal-title":"IEEE Computer"},{"issue":"#6","key":"10.1016\/0165-6074(88)90057-9_BIB26","first-page":"423","article-title":"SLIDE: An I\/O Hardware Description Language","volume":"C-30","author":"Parker","year":"1980","journal-title":"IEEE Computer"},{"key":"10.1016\/0165-6074(88)90057-9_BIB27","doi-asserted-by":"crossref","first-page":"549","DOI":"10.1016\/0165-6074(86)90091-8","article-title":"SMAX - A Conlan Member Language for Verifiable Hardware Descriptions","author":"Eveking","year":"1986","journal-title":"Microprocessing & Microcomputing"},{"key":"10.1016\/0165-6074(88)90057-9_BIB28","series-title":"Proc. CHDL and Applications","first-page":"31","article-title":"WISLAN - A Conlan Member for Gate Array Design","author":"Engh","year":"1985"},{"key":"10.1016\/0165-6074(88)90057-9_BIB29","series-title":"Proc. DA Conf.","first-page":"17","article-title":"Zeus: A Hardware Description Language for VLSI","author":"Lieberherr","year":"1983"},{"key":"10.1016\/0165-6074(88)90057-9_BIB30","series-title":"Symp. on Microcomp. and Microproc. Appl.","first-page":"435","article-title":"A personal hierarchical design system for digital hardware","author":"Raud","year":"1987"},{"key":"10.1016\/0165-6074(88)90057-9_BIB31","first-page":"117","article-title":"A Distributed System for VLSI Design","author":"Loomis","year":"1983"},{"key":"10.1016\/0165-6074(88)90057-9_BIB32","first-page":"875","article-title":"Technology Transfer Between VLSI Design and Software Engineering: CAD Tools and Design Methodologies","author":"Smith","year":"1986"},{"key":"10.1016\/0165-6074(88)90057-9_BIB33","first-page":"122","article-title":"Conversations with an Intelligent Chaos","volume":"#5","author":"Rauzino","year":"1982","journal-title":"Datamation"},{"key":"10.1016\/0165-6074(88)90057-9_BIB34","first-page":"88","article-title":"Methodical Aspects of Logic Synthesis","author":"Lipp","year":"1983"},{"key":"10.1016\/0165-6074(88)90057-9_BIB35","series-title":"Proc. IEEE Conf. CAD","first-page":"640","article-title":"Computer-Aided Design of Integrated Circuits Using IBM PC","author":"Nelson","year":"1984"},{"issue":"#1","key":"10.1016\/0165-6074(88)90057-9_BIB36","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1109\/MS.1984.233394","article-title":"Transforming Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Environment: A First Experiment","author":"Organick","year":"1984","journal-title":"IEEE Software"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607488900579?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607488900579?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2023,4,26]],"date-time":"2023-04-26T21:31:37Z","timestamp":1682544697000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607488900579"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1988,8]]},"references-count":36,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1988,8]]}},"alternative-id":["0165607488900579"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(88)90057-9","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1988,8]]}}}