{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T03:55:06Z","timestamp":1648698906724},"reference-count":9,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1988,8,1]],"date-time":"1988-08-01T00:00:00Z","timestamp":586396800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1988,8]]},"DOI":"10.1016\/0165-6074(88)90059-2","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"233-238","source":"Crossref","is-referenced-by-count":6,"title":["CMOS fault modeling, test generation and design for testability"],"prefix":"10.1016","volume":"24","author":[{"given":"C","family":"Matth\u00e4us","sequence":"first","affiliation":[]},{"given":"B","family":"Kr\u00fcger-Sprengel","sequence":"additional","affiliation":[]},{"given":"C","family":"Glowacz","sequence":"additional","affiliation":[]},{"given":"U","family":"H\u00fcbner","sequence":"additional","affiliation":[]},{"given":"H.T","family":"Vierhaus","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(88)90059-2_BIB1","doi-asserted-by":"crossref","first-page":"1449","DOI":"10.1002\/j.1538-7305.1978.tb02106.x","article-title":"Fault Modeling and Simulation of CMOS and MOS Integrated Circuits","author":"Wadsack","year":"1978","journal-title":"Bell Syst. Tech. J."},{"key":"10.1016\/0165-6074(88)90059-2_BIB2","doi-asserted-by":"crossref","first-page":"527","DOI":"10.1109\/TC.1980.1675614","article-title":"Physical Versus Logical Fault Models in MOS LSI Circuits, Impact on Their Testability","volume":"C-29","author":"Galiay","year":"1980","journal-title":"IEEE Trans. Comp."},{"key":"10.1016\/0165-6074(88)90059-2_BIB3","doi-asserted-by":"crossref","first-page":"424","DOI":"10.1109\/TC.1986.1676825","article-title":"Testable Realization for FET Stuck Open Faults in CMOS Combinational Logic Circuits","volume":"C-35","author":"Reddy","year":"1986","journal-title":"IEEE Trans. Comp."},{"key":"10.1016\/0165-6074(88)90059-2_BIB4","series-title":"Proc. 3rd E.I.S.-Workshop","article-title":"Fault Modeling and Test Pattern Generation for Static CMOS Circuits","volume":"126","author":"H\u00fcbner","year":"1987"},{"key":"10.1016\/0165-6074(88)90059-2_BIB5","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MDT.1987.295148","article-title":"Designing CMOS Circuits for Switch Level Testability","volume":"Vol. 4","author":"Liu","year":"1987","journal-title":"IEEE Design & Test"},{"key":"10.1016\/0165-6074(88)90059-2_BIB6","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1109\/MDT.1986.295040","article-title":"Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops","volume":"Vol. 3","author":"Reddy","year":"1986","journal-title":"IEEE Design & Test"},{"key":"10.1016\/0165-6074(88)90059-2_BIB7","article-title":"Entwurf, Optimierung und Implementierung gut testbarer Flip-Flops und Scan-Path-Elemente in CMOS Technik","author":"Glowacz","year":"1987"},{"key":"10.1016\/0165-6074(88)90059-2_BIB8","unstructured":"H. T. Vierhaus, \u201cRule-Based Design for Testability \u2014 the EXTEST Approach\u201d, Proc. CompEuro '87, pp. 949\u2013952"},{"key":"10.1016\/0165-6074(88)90059-2_BIB9","series-title":"Proc. 20th Des. Aut. Conf.","first-page":"50","article-title":"On Fault Detection in CMOS Logic Networks","author":"Chiang","year":"1983"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607488900592?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607488900592?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T09:54:25Z","timestamp":1551088465000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607488900592"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1988,8]]},"references-count":9,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1988,8]]}},"alternative-id":["0165607488900592"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(88)90059-2","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1988,8]]}}}