{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T03:30:50Z","timestamp":1648611050327},"reference-count":31,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1988,8,1]],"date-time":"1988-08-01T00:00:00Z","timestamp":586396800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1988,8]]},"DOI":"10.1016\/0165-6074(88)90081-6","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"371-378","source":"Crossref","is-referenced-by-count":3,"title":["Formal specification and verification of microprocessor systems"],"prefix":"10.1016","volume":"24","author":[{"given":"Jeffrey J","family":"Joyce","sequence":"first","affiliation":[]}],"member":"78","reference":[{"issue":"No. 1","key":"10.1016\/0165-6074(88)90081-6_BIB1","doi-asserted-by":"crossref","DOI":"10.1109\/TC.1981.6312154","article-title":"Instruction Set Processor Specification (ISPS): The Notation and its Application","volume":"Vol. C-30","author":"Barbacci","year":"1981","journal-title":"IEEE Transactions on Computers"},{"issue":"No. 1\u20133","key":"10.1016\/0165-6074(88)90081-6_BIB2","article-title":"VERIFY: A Program for Proving Correctness of Digital Hardware Designs","volume":"Vol. 24","author":"Barrow","year":"1984","journal-title":"Artificial Intelligence"},{"key":"10.1016\/0165-6074(88)90081-6_BIB3","article-title":"The Formal Specification of a Microprocessor Instruction Set","author":"Bowen","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB4","article-title":"A Switch-Level Simulation Model for Integrated Logic Circuits","author":"Bryant","year":"1981"},{"key":"10.1016\/0165-6074(88)90081-6_BIB5","article-title":"Executing Behavioural Definitions in Higher Order Logic","author":"Camilleri","year":"1988"},{"key":"10.1016\/0165-6074(88)90081-6_BIB6","doi-asserted-by":"crossref","DOI":"10.1016\/0743-1066(87)90022-7","article-title":"Logic Programming and Digital Circuit Analysis","volume":"Vol. 4","author":"Clocksin","year":"1987","journal-title":"The Journal of Logic Programming"},{"key":"10.1016\/0165-6074(88)90081-6_BIB7","series-title":"Proceedings of the Workshop on Hardware Verification","article-title":"A Proof of Correctness of the Viper Microprocessor: The First Level","author":"Cohn","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB8","series-title":"Proceedings of the Workshop on Hardware Verification","article-title":"Formal Validation of an Integrated Circuit Design Style","author":"Dhingra","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB9","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-09724-4","article-title":"Edinburgh LCF: An Mechanised Logic of Computation","author":"Gordon","year":"1979"},{"key":"10.1016\/0165-6074(88)90081-6_BIB10","series-title":"Technical Report No. 42","article-title":"Proving a Computer Correct using the LCF LSM Hardware Verification System","author":"Gordon","year":"1983"},{"key":"10.1016\/0165-6074(88)90081-6_BIB11","series-title":"Proceedings of the 1985 Edinburgh Conferences on VLSI","article-title":"Why Higher-Order Logic is a Good Formalism for Specifying and Verifying Hardware","author":"Gordon","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB12","series-title":"Proceedings of the Workshop on Hardware Verification","article-title":"A Proof Generating System for Higher-Order Logic","author":"Gordon","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB13","series-title":"Functional Programming","author":"Henderson","year":"1980"},{"key":"10.1016\/0165-6074(88)90081-6_BIB14","article-title":"Application of Formal Methods to Digital System Design","author":"Herbert","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB15","article-title":"High-Level Microprogramming Support Embedded in Silicon","volume":"Vol. 135","author":"Hobson","year":"1988"},{"key":"10.1016\/0165-6074(88)90081-6_BIB16","article-title":"FM8501: A Verified Microprocessor","author":"Hunt","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB17","article-title":"Proving a Computer Correct in Higher Order Logic","author":"Joyce","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB18","series-title":"Proceedings of the Workshop on Hardware Verification","article-title":"Formal Verification and Implementation of a Microprocessor","author":"Joyce","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB19","article-title":"Hardware Verification of VLSI Regular Structures","author":"Joyce","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB20","series-title":"Multi-Level Verification of a Simple Microprocessor","author":"Joyce","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB21","article-title":"Reasoning about the Function and Timing of Integrated Circuits with Prolog and Temporal Logic","author":"Leeser","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB22","article-title":"Formal Verification of the IMS T800 Microprocessor","author":"May","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB23","series-title":"Proceedings of the Workshop on Hardware Verification","article-title":"Abstraction Mechanisms for Hardware Verification","author":"Melham","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB24","article-title":"Behavioural Description and VLSI Verification","volume":"Vol. 133","author":"Milne","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB25","article-title":"Reasoning about Digital Circuits","author":"Moszkowski","year":"1983"},{"key":"10.1016\/0165-6074(88)90081-6_BIB26","article-title":"SPICE2: A Computer Program to Simulate Semiconductor Circuits","author":"Nagel","year":"1975"},{"key":"10.1016\/0165-6074(88)90081-6_BIB27","series-title":"Logic and Computation","author":"Paulson","year":"1987"},{"key":"10.1016\/0165-6074(88)90081-6_BIB28","article-title":"BSPL: A Language for Describing the Behaviour of Synchronous Hardware","author":"Richards","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB29","article-title":"Design and Verification of Regular Synchronous Circuits","volume":"Vol. 133","author":"Sheeran","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB30","article-title":"Formal Multilevel Hierarchical Verification of Synchronous MOS VLSI Circuits","author":"Weise","year":"1986"},{"key":"10.1016\/0165-6074(88)90081-6_BIB31","series-title":"Proceedings of the Workshop on Hardware Verification","article-title":"Models and Logic of MOS Circuits","author":"Winskel","year":"1987"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607488900816?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607488900816?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T09:54:02Z","timestamp":1551088442000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607488900816"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1988,8]]},"references-count":31,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1988,8]]}},"alternative-id":["0165607488900816"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(88)90081-6","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1988,8]]}}}