{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T10:49:39Z","timestamp":1648637379298},"reference-count":6,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1990,3,1]],"date-time":"1990-03-01T00:00:00Z","timestamp":636249600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1990,3]]},"DOI":"10.1016\/0165-6074(90)90163-4","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T13:14:48Z","timestamp":1062594888000},"page":"139-143","source":"Crossref","is-referenced-by-count":2,"title":["Area compaction in silicon structures for neural net implementation"],"prefix":"10.1016","volume":"28","author":[{"given":"F.","family":"Distante","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.G.","family":"Sami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Stefanelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.Storti","family":"Gajani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(90)90163-4_BIB1","series-title":"Proc. ISCAS 1989","first-page":"82","article-title":"A study of regular architectures for digital implementation of neural networks","author":"Suzuki","year":"1989"},{"key":"10.1016\/0165-6074(90)90163-4_BIB2","series-title":"Proc. 2nd Workshop on Neural Networks and Parallel Architectures","article-title":"Alternative approaches for mapping neural networks onto silicon","author":"Distante","year":"1989"},{"key":"10.1016\/0165-6074(90)90163-4_BIB3","series-title":"Proc. ISCAS 1989","first-page":"445","article-title":"Digital VLSI architectures for neural networks","author":"Kung","year":"1989"},{"key":"10.1016\/0165-6074(90)90163-4_BIB4","series-title":"Proc. Int'l Conf. on Systolic Arrays","first-page":"163","article-title":"Parallel architectures for artificial neural nets","author":"Kung","year":"1988"},{"key":"10.1016\/0165-6074(90)90163-4_BIB5","series-title":"Proc. ICS 89","first-page":"279","article-title":"Multistage interleaved architecture for implementation of neural networks","author":"Distante","year":"1989"},{"key":"10.1016\/0165-6074(90)90163-4_BIB6","doi-asserted-by":"crossref","first-page":"533","DOI":"10.1109\/TCS.1986.1085953","article-title":"Simple \u2018neural\u2019 optimization networks: an A\/D Converter, Signals Decision Circuit, and Linear Programming Circuit","volume":"CAS-33","author":"Tank","year":"1986","journal-title":"IEEE Trans. Circuit an Systems"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607490901634?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607490901634?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T04:59:25Z","timestamp":1551070765000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607490901634"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990,3]]},"references-count":6,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1990,3]]}},"alternative-id":["0165607490901634"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(90)90163-4","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1990,3]]}}}