{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T01:53:36Z","timestamp":1648691616985},"reference-count":7,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1990,3,1]],"date-time":"1990-03-01T00:00:00Z","timestamp":636249600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1990,3]]},"DOI":"10.1016\/0165-6074(90)90196-g","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"319-322","source":"Crossref","is-referenced-by-count":0,"title":["A new concept for chip architecture design \u2014 Interactive architecture compilation from system specification to register-transfer algorithms"],"prefix":"10.1016","volume":"28","author":[{"given":"Uwe","family":"Wienkop","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(90)90196-G_BIB1","series-title":"Proc. of VLSI 89","article-title":"CALLAS - Conversion of Algorithms to Library Adaptable Structures","author":"Duzy","year":"1989"},{"key":"10.1016\/0165-6074(90)90196-G_BIB2","unstructured":"Synopsis Corporation: Logic Synthesis with Verilog and Synopsis Synopsis product presentation handouts"},{"key":"10.1016\/0165-6074(90)90196-G_BIB3","series-title":"Proc. 25th Design Automation Conference","first-page":"654","article-title":"SMART: Tools and Methods for Synthesis of VLSI-Chips with Processor Architecture","author":"Bergstr\u00e4sser","year":"1988"},{"key":"10.1016\/0165-6074(90)90196-G_BIB4","series-title":"Intelligent Designing means Intelligent Silicon Compilation","author":"Silicon Compilers Corporation","year":"1987"},{"key":"10.1016\/0165-6074(90)90196-G_BIB5","unstructured":"Gateway Design Automation Corporation: Hardware Description Languages for Design Verification and Test Gateway product presentation handouts"},{"key":"10.1016\/0165-6074(90)90196-G_BIB6","unstructured":"H. Endriss, G. Klein-Hessling, G. Lawitzky, B. Schallenberger: Fast Evaluation of Design Alternatives \u2014 A new Approach for Exploratory Chip Design Microprocessing and Microprogramming 88"},{"key":"10.1016\/0165-6074(90)90196-G_BIB7","unstructured":"U. Wienkop: High level estimation - Characterizing Algorithmic Properties In preparation"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749090196G?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749090196G?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T09:58:44Z","timestamp":1551088724000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016560749090196G"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990,3]]},"references-count":7,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1990,3]]}},"alternative-id":["016560749090196G"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(90)90196-g","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1990,3]]}}}