{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T03:54:55Z","timestamp":1648698895439},"reference-count":24,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1990,8,1]],"date-time":"1990-08-01T00:00:00Z","timestamp":649468800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1990,8]]},"DOI":"10.1016\/0165-6074(90)90242-2","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T13:14:48Z","timestamp":1062594888000},"page":"207-214","source":"Crossref","is-referenced-by-count":10,"title":["A new solution of coherence protocol for tightly coupled multiprocessor systems"],"prefix":"10.1016","volume":"30","author":[{"given":"Cosimo Antonio","family":"Prete","sequence":"first","affiliation":[]}],"member":"78","reference":[{"issue":"n. 1","key":"10.1016\/0165-6074(90)90242-2_BIB1","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1147\/rd.261.0012","article-title":"IBM 3081 processor unit: Design considerations and design process","volume":"vol. 26","author":"Gustafson","year":"1982","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/0165-6074(90)90242-2_BIB2","series-title":"Proc. of the 3rd Annual Symp. on Computer Architecture","first-page":"155","article-title":"Cache memories for PDP-11 family computers","author":"Strecker","year":"1976"},{"issue":"n. 3","key":"10.1016\/0165-6074(90)90242-2_BIB3","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1145\/356887.356892","article-title":"Cache memories","volume":"vol. 14","author":"Smith","year":"1982","journal-title":"ACM Computing Surveys"},{"key":"10.1016\/0165-6074(90)90242-2_BIB4","first-page":"937","article-title":"On modeling program behavior","volume":"vol. 40","author":"Denning","year":"1972"},{"key":"10.1016\/0165-6074(90)90242-2_BIB5","series-title":"Multiprocessors: A comparative study","author":"Satyanarayanan","year":"1980"},{"issue":"n. 2","key":"10.1016\/0165-6074(90)90242-2_BIB6","doi-asserted-by":"crossref","first-page":"121","DOI":"10.1145\/356810.356813","article-title":"Experience using multiprocessor systems: A status report","volume":"vol. 12","author":"Jones","year":"1980","journal-title":"ACM Computing Surveys"},{"key":"10.1016\/0165-6074(90)90242-2_BIB7","series-title":"Computer architecture and parallel processing","author":"Hwang","year":"1984"},{"key":"10.1016\/0165-6074(90)90242-2_BIB8","first-page":"217","article-title":"Architecture of the MuTEAM system","volume":"vol. 134","author":"Corsini","year":"1987"},{"issue":"n. 1\u20132","key":"10.1016\/0165-6074(90)90242-2_BIB9","first-page":"61","article-title":"Cache memory optimization to reduce processor\/memory traffic","volume":"Vol. 2","author":"Goodman","year":"1987","journal-title":"Journal of VLSI and Computer Systems"},{"issue":"n. 1","key":"10.1016\/0165-6074(90)90242-2_BIB10","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1109\/40.521","article-title":"The Balance multiprocessor systems","volume":"vol. 8","author":"Thakkar","year":"1988","journal-title":"IEEE Micro"},{"key":"10.1016\/0165-6074(90)90242-2_BIB11","series-title":"Proc. of the 12th Int. Symp. on Computer Architecture","first-page":"276","article-title":"Implementing a cache consistency protocol","author":"Katz","year":"1985"},{"key":"10.1016\/0165-6074(90)90242-2_BIB12","series-title":"Proc. of the 11th Int. Symp. on Computer Architecture","first-page":"348","article-title":"A low overhead coherence solution for multiprocessors with private cache memories","author":"Papamarcos","year":"1984"},{"key":"10.1016\/0165-6074(90)90242-2_BIB13","series-title":"Proc. of the 10th Int. Symp. on Computer Architecture","first-page":"124","article-title":"Using cache memory to reduce processor-memory traffic","author":"Goodman","year":"1983"},{"issue":"n. 8","key":"10.1016\/0165-6074(90)90242-2_BIB14","doi-asserted-by":"crossref","first-page":"909","DOI":"10.1109\/12.2243","article-title":"Firefly: a multiprocessor workstation","volume":"vol. C-37","author":"Thacker","year":"1988","journal-title":"IEEE Trans. Computers"},{"key":"10.1016\/0165-6074(90)90242-2_BIB15","series-title":"Proc. of the Thirtieth IEEE Int. Conf.","first-page":"118","article-title":"The architecture of the dragon","author":"Monier","year":"1985"},{"key":"10.1016\/0165-6074(90)90242-2_BIB16","series-title":"Proc. 4th Annual Symp. Computer Architecture","first-page":"179","article-title":"Reduction of memory interference in multiprocessor systems","author":"Hoogendoom","year":"1977"},{"key":"10.1016\/0165-6074(90)90242-2_BIB17","first-page":"749","article-title":"Cache system design in the tightly coupled multiprocessor system","volume":"vol. 45","author":"Tang","year":"1976"},{"issue":"n. 12","key":"10.1016\/0165-6074(90)90242-2_BIB18","doi-asserted-by":"crossref","first-page":"1112","DOI":"10.1109\/TC.1978.1675013","article-title":"A new solution to coherence problems in multicache systems","volume":"vol. C-27","author":"Censier","year":"1978","journal-title":"IEEE Trans. Computers"},{"issue":"n. 11","key":"10.1016\/0165-6074(90)90242-2_BIB19","doi-asserted-by":"crossref","first-page":"1083","DOI":"10.1109\/TC.1982.1675925","article-title":"Effects of cache coherency in multiprocessors","volume":"vol. C-31","author":"Dubois","year":"1982","journal-title":"IEEE Trans. Computers"},{"key":"10.1016\/0165-6074(90)90242-2_BIB20","series-title":"Proc. of the Int. Conf. on Parallel Processing","first-page":"332","article-title":"Coherence problem in a multicache system","author":"Yen","year":"1982"},{"key":"10.1016\/0165-6074(90)90242-2_BIB21","series-title":"Proc. of the 11th Int. Symp. on Computer Architecture","first-page":"355","article-title":"An economical solution to the cache coherence problem","author":"Archibald","year":"1984"},{"key":"10.1016\/0165-6074(90)90242-2_BIB22","first-page":"273","article-title":"Cache coherence protocols: Evaluation using a multiprocessor simulation model","volume":"vol. 4","author":"Archibald","year":"1986"},{"key":"10.1016\/0165-6074(90)90242-2_BIB23","series-title":"Proc. of the 13th Int. Symp. on Computer Architecture","first-page":"414","article-title":"A class of compatible cache consistency protocols and their support by the IEEE Futurebus","author":"Sweazey","year":"1986"},{"key":"10.1016\/0165-6074(90)90242-2_BIB24","series-title":"Proc. of the Third Int. Symp. on Computer and Information Sciences","first-page":"693","article-title":"An example of cache memory design for multiprocessor systems based on CLIPPER FAIRCHILD microprocessor","author":"Cinquini","year":"1988"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607490902422?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607490902422?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T05:20:48Z","timestamp":1551072048000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607490902422"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990,8]]},"references-count":24,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1990,8]]}},"alternative-id":["0165607490902422"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(90)90242-2","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1990,8]]}}}