{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T07:48:21Z","timestamp":1648712901047},"reference-count":18,"publisher":"Elsevier BV","issue":"5","license":[{"start":{"date-parts":[[1991,3,1]],"date-time":"1991-03-01T00:00:00Z","timestamp":667785600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1991,3]]},"DOI":"10.1016\/0165-6074(91)90004-d","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"293-302","source":"Crossref","is-referenced-by-count":3,"title":["Realization of multilayer Boolean neural networks with logic gate array"],"prefix":"10.1016","volume":"29","author":[{"given":"Veselko","family":"Gu\u0161tin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrej","family":"Dobnikar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(91)90004-D_BIB1","first-page":"216","article-title":"Neural network model of learning and adaptation","volume":"22D","author":"Denker","year":"1986","journal-title":"Physica"},{"key":"10.1016\/0165-6074(91)90004-D_BIB2","author":"Rumelhart","year":"1987"},{"issue":"23","key":"10.1016\/0165-6074(91)90004-D_BIB3","doi-asserted-by":"crossref","first-page":"5077","DOI":"10.1364\/AO.26.005077","article-title":"Electronic neural network chips","volume":"26","author":"Jackel","year":"1987","journal-title":"Applied Optics"},{"key":"10.1016\/0165-6074(91)90004-D_BIB4","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/2.29","article-title":"Neural nets for adaptive filtering and adaptive pattern recognition","author":"Windrow","year":"1988","journal-title":"IEEE Comput."},{"issue":"23","key":"10.1016\/0165-6074(91)90004-D_BIB5","doi-asserted-by":"crossref","first-page":"5077","DOI":"10.1364\/AO.26.005077","article-title":"Electronic neural network chips","author":"Jackel","year":"1987","journal-title":"Applied Optics"},{"key":"10.1016\/0165-6074(91)90004-D_BIB6","doi-asserted-by":"crossref","first-page":"41","DOI":"10.1109\/2.30","article-title":"VLSI implementation of a neural network model","author":"Graf","year":"1988","journal-title":"Computer"},{"issue":"7","key":"10.1016\/0165-6074(91)90004-D_BIB7","doi-asserted-by":"crossref","first-page":"1180","DOI":"10.1109\/29.1645","article-title":"Implementing neural nets with programmable logic","volume":"36","author":"Vidal","year":"1988","journal-title":"IEEE Trans. Acoust. Speech Signed Process."},{"issue":"7","key":"10.1016\/0165-6074(91)90004-D_BIB8","doi-asserted-by":"crossref","first-page":"667","DOI":"10.1109\/TC.1968.227442","article-title":"Nets of variable-threshold threshold elements","volume":"C-17","author":"Meisel","year":"1968","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0165-6074(91)90004-D_BIB9","doi-asserted-by":"crossref","first-page":"385","DOI":"10.1109\/TC.1968.229389","article-title":"On autonomous logic nets of threshold elements","author":"Yajima","year":"1968","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0165-6074(91)90004-D_BIB10","author":"Yajima","year":"1986"},{"key":"10.1016\/0165-6074(91)90004-D_BIB11","article-title":"A logical processing of digital signals","author":"Hurst","year":"1978","journal-title":"Complex Systems Engineering Ser."},{"key":"10.1016\/0165-6074(91)90004-D_BIB12","series-title":"Analog VLSI and Neural Systems","author":"Mead","year":"1989"},{"key":"10.1016\/0165-6074(91)90004-D_BIB13","series-title":"First IEE Internat. Conf. on Artificial neural Networks","article-title":"Silicon implementation of neural networks","author":"Murray","year":"1989"},{"key":"10.1016\/0165-6074(91)90004-D_BIB14","series-title":"First IEE Internat. Conf. on Artificial Neural Networks","article-title":"The implementation of hardware neural net systems","author":"Myers","year":"1989"},{"key":"10.1016\/0165-6074(91)90004-D_BIB15","series-title":"First IEE Internat. Conf. on Artificial Neural Networks","article-title":"A general purpose digital architecture for neural network simulations","author":"Duranton","year":"1989"},{"key":"10.1016\/0165-6074(91)90004-D_BIB16","series-title":"Fourth Internat. Conf. on Superconputing and Third World Supercomputing Exhibition","first-page":"279","article-title":"Multistage interleaved architectures for implementation of neural networks","author":"Distante","year":"1989"},{"key":"10.1016\/0165-6074(91)90004-D_BIB17","article-title":"Image frame processing with neural networks","author":"Dobnikar","year":"1989"},{"key":"10.1016\/0165-6074(91)90004-D_BIB18","series-title":"Adaptive Pattern Recognition and Neural Networks","author":"Pao","year":"1989"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749190004D?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749190004D?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T10:00:04Z","timestamp":1551088804000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016560749190004D"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,3]]},"references-count":18,"journal-issue":{"issue":"5","published-print":{"date-parts":[[1991,3]]}},"alternative-id":["016560749190004D"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(91)90004-d","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1991,3]]}}}