{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T16:29:27Z","timestamp":1649003367917},"reference-count":11,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1992,9,1]],"date-time":"1992-09-01T00:00:00Z","timestamp":715305600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1992,9]]},"DOI":"10.1016\/0165-6074(92)90314-w","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T04:56:10Z","timestamp":1060318570000},"page":"181-186","source":"Crossref","is-referenced-by-count":5,"title":["A behavioral approach to testability analysis for neural networks"],"prefix":"10.1016","volume":"35","author":[{"given":"Vincenzo","family":"Piuri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mariagiovanna","family":"Sami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donatella","family":"Sciuto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Renato","family":"Stefanelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(92)90314-W_BIB1","article-title":"Neural networks and physical systems with emergent collective computational abilities","volume":"vol. 79","author":"Hopfield","year":"1982"},{"key":"10.1016\/0165-6074(92)90314-W_BIB2","series-title":"Analog VLSI and neural systems","author":"Mead","year":"1989"},{"key":"10.1016\/0165-6074(92)90314-W_BIB3","series-title":"Proc. Systolic Arrays 1988","article-title":"Parallel architectures for artificial neural nets","author":"Kung","year":"1988"},{"key":"10.1016\/0165-6074(92)90314-W_BIB4","series-title":"Proc. Int'l Workshop on VLSI for artificial intelligence and neural networks","article-title":"A VLSI implementation of a generic systolic synaptic building block for neural networks","author":"Lehmann","year":"1990"},{"key":"10.1016\/0165-6074(92)90314-W_BIB5","series-title":"Proc. IFIP Workshop on Sicilicon Architectures for Neural Networks","article-title":"A compact and fast silicon implementation for layered neural nets","author":"Distante","year":"1990"},{"key":"10.1016\/0165-6074(92)90314-W_BIB6","series-title":"Proc. IFIP Workshop on Silicon Architectures for Neural Networks","article-title":"VLSI design of a neural signal processor","author":"Beichter","year":"1990"},{"key":"10.1016\/0165-6074(92)90314-W_BIB7","series-title":"Proc. IJCNN 1990","article-title":"Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed of 576 digital neurons","author":"Yasunaga","year":"1990"},{"issue":"N. 2","key":"10.1016\/0165-6074(92)90314-W_BIB8","doi-asserted-by":"crossref","DOI":"10.1007\/BF00137388","article-title":"A Hierarchical Test Generation Methodology for Digital Circuits","volume":"Vol. 1","author":"Bhattacharya","year":"1990","journal-title":"Journal of Electronic Testing"},{"key":"10.1016\/0165-6074(92)90314-W_BIB9","series-title":"Proc. Int'l Conf. on Wafer-Scale Integration","article-title":"High-level design of algorithm-driven architectures: the testability and diagnosability issue","author":"Antola","year":"1992"},{"key":"10.1016\/0165-6074(92)90314-W_BIB10","series-title":"Proc. 2nd Int'l Conf. on Microelectronics for Neural Networks","article-title":"Silicon compilation of neuro-ASICs supported by a distributed and synchronous neural network architecture","author":"Alla","year":"1991"},{"key":"10.1016\/0165-6074(92)90314-W_BIB11","series-title":"Proc. Int'l Workshop on Defect and Fault Tolerance in VLSI Systems","article-title":"Behavioral modeling of physical defects in VLSI neural networks","author":"Feltham","year":"1990"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749290314W?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749290314W?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T01:52:56Z","timestamp":1552614776000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016560749290314W"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1992,9]]},"references-count":11,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1992,9]]}},"alternative-id":["016560749290314W"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(92)90314-w","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1992,9]]}}}