{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,16]],"date-time":"2023-05-16T15:53:04Z","timestamp":1684252384698},"reference-count":9,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1992,9,1]],"date-time":"1992-09-01T00:00:00Z","timestamp":715305600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1992,9]]},"DOI":"10.1016\/0165-6074(92)90366-f","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T00:56:10Z","timestamp":1060304170000},"page":"539-544","source":"Crossref","is-referenced-by-count":1,"title":["Dependence graph transformations in the design of processor arrays for matrix multiplications"],"prefix":"10.1016","volume":"35","author":[{"given":"Roman","family":"Wyrzykowski","sequence":"first","affiliation":[]},{"given":"Yurij","family":"Kanevski","sequence":"additional","affiliation":[]},{"given":"Sergej","family":"Ovramenko","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(92)90366-F_BIB1","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","article-title":"Why Systolic Architectures?","author":"Kung","year":"1982","journal-title":"Computer"},{"key":"10.1016\/0165-6074(92)90366-F_BIB2","series-title":"VLSI Array Processors","author":"Kung","year":"1988"},{"key":"10.1016\/0165-6074(92)90366-F_BIB3","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TC.1986.1676652","article-title":"Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays","volume":"35","author":"Moldovan","year":"1986","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0165-6074(92)90366-F_BIB4","first-page":"1304","article-title":"Array Architectures for Iterative Algorithms","volume":"75","author":"Jagadish","year":"1987"},{"key":"10.1016\/0165-6074(92)90366-F_BIB5","series-title":"Systolic Algorithms and Architectures","author":"Quinton","year":"1991"},{"key":"10.1016\/0165-6074(92)90366-F_BIB6","series-title":"Systolic Arrays","author":"Kanevsky","year":"1992"},{"key":"10.1016\/0165-6074(92)90366-F_BIB7","unstructured":"Wyrzykowski, R. and Ovramenko S.G., A Flexible Systolic Architecture for VLSI FIR Filters, IEE Proc.: Pt. E, in print."},{"key":"10.1016\/0165-6074(92)90366-F_BIB8","first-page":"149","article-title":"Array Architectures for Iterative Matrix Calculations","volume":"134","author":"El-Amawy","year":"1987"},{"key":"10.1016\/0165-6074(92)90366-F_BIB9","doi-asserted-by":"crossref","first-page":"347","DOI":"10.1016\/0020-0255(88)90010-2","article-title":"Multilayered Array Computing","volume":"45","author":"Kak","year":"1988","journal-title":"Information Sciences"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749290366F?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749290366F?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,14]],"date-time":"2019-03-14T21:52:09Z","timestamp":1552600329000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016560749290366F"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1992,9]]},"references-count":9,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1992,9]]}},"alternative-id":["016560749290366F"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(92)90366-f","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1992,9]]}}}