{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T00:31:24Z","timestamp":1649118684685},"reference-count":7,"publisher":"Elsevier BV","issue":"2-5","license":[{"start":{"date-parts":[[1993,12,1]],"date-time":"1993-12-01T00:00:00Z","timestamp":754704000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1993,12]]},"DOI":"10.1016\/0165-6074(93)90098-6","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T13:14:48Z","timestamp":1062594888000},"page":"245-248","source":"Crossref","is-referenced-by-count":0,"title":["Testability enhancement using physical design rules in a CMOS cell library"],"prefix":"10.1016","volume":"39","author":[{"given":"F.C.","family":"Blom","sequence":"first","affiliation":[]},{"given":"J.","family":"Oliver","sequence":"additional","affiliation":[]},{"given":"M.","family":"Rull\u00e1n","sequence":"additional","affiliation":[]},{"given":"C.","family":"Ferrer","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"n\u00b02","key":"10.1016\/0165-6074(93)90098-6_BIB1","doi-asserted-by":"crossref","first-page":"1449","DOI":"10.1002\/j.1538-7305.1978.tb02106.x","article-title":"Fault Modeling and Logic Simulation of CMOS and NMOS Integrated Circuits","volume":"vol. 57","author":"Wadsack","year":"1978","journal-title":"Bell Syst., Tech. Journal"},{"key":"10.1016\/0165-6074(93)90098-6_BIB2","series-title":"Proc. 24 Design Automation Conf. (DAC)","first-page":"173","article-title":"Realistic Fault Modeling for VLSI Testing","author":"Maly","year":"1987"},{"key":"10.1016\/0165-6074(93)90098-6_BIB3","series-title":"European Test Conference","first-page":"101","article-title":"Layout-driven testability enhancement","author":"Teixeira","year":"1991"},{"key":"10.1016\/0165-6074(93)90098-6_BIB4","series-title":"Proc. Compeuro","first-page":"949","article-title":"Rule-based design for testability- The extest approach","author":"Vierhaus","year":"1987"},{"key":"10.1016\/0165-6074(93)90098-6_BIB5","series-title":"European Test Conference","first-page":"143","article-title":"Fault modeling of Gate Oxide Shorts, Floating Gate and Bridging Failures in CMOS Circuits","author":"Champac","year":"1991"},{"key":"10.1016\/0165-6074(93)90098-6_BIB6","series-title":"Workshop Design for Testability","article-title":"Layout-Level Design for Testability Strategy Applied to a CMOS Cell Library","author":"Blom","year":"1993"},{"key":"10.1016\/0165-6074(93)90098-6_BIB7","series-title":"24th ACM\/IEEE Design Automation Conference","first-page":"829","article-title":"Optimal layout to avoid CMOS stuck-open faults","author":"Koeppe","year":"1987"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607493900986?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607493900986?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T05:26:08Z","timestamp":1551072368000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607493900986"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,12]]},"references-count":7,"journal-issue":{"issue":"2-5","published-print":{"date-parts":[[1993,12]]}},"alternative-id":["0165607493900986"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(93)90098-6","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1993,12]]}}}