{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T11:17:41Z","timestamp":1672571861583},"reference-count":27,"publisher":"Elsevier BV","issue":"1-5","license":[{"start":{"date-parts":[[1993,9,1]],"date-time":"1993-09-01T00:00:00Z","timestamp":746841600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1993,9]]},"DOI":"10.1016\/0165-6074(93)90132-5","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"99-107","source":"Crossref","is-referenced-by-count":5,"title":["The memory hierarchy of the CHESS computer"],"prefix":"10.1016","volume":"38","author":[{"given":"D.","family":"Lioupis","sequence":"first","affiliation":[]},{"given":"N.","family":"Kanellopoulos","sequence":"additional","affiliation":[]},{"given":"M.","family":"Stefanidakis","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(93)90132-5_BIB1","series-title":"Proceedings of the 17th International Symposium on Computer Architecture","article-title":"Weak Ordering \u2014 A New Definition","author":"Adve","year":"1990"},{"key":"10.1016\/0165-6074(93)90132-5_BIB2","series-title":"Proceedings of ACM Sigmetrics","article-title":"Memory-Reference Characteristics of Multiprocessor Applications under MACH","author":"Agarwal","year":"1988"},{"key":"10.1016\/0165-6074(93)90132-5_BIB3","series-title":"Proceedings of the 18th International Symposium on Computer Architecture","article-title":"Detecting Data Races on Weak Memory Systems","author":"Adve","year":"1991"},{"key":"10.1016\/0165-6074(93)90132-5_BIB4","doi-asserted-by":"crossref","DOI":"10.1145\/6513.6514","article-title":"An Evaluation of Cache Coherence Solutions in Shared-Bus Multiprocessors","author":"Archibald","year":"1986","journal-title":"ACM Transactions on Computer Systems"},{"key":"10.1016\/0165-6074(93)90132-5_BIB5","doi-asserted-by":"crossref","DOI":"10.1126\/science.228.4698.462","article-title":"Multis: A New Class of Multiprocessor Computers","author":"Bell","year":"1985","journal-title":"Science"},{"key":"10.1016\/0165-6074(93)90132-5_BIB6","article-title":"Coherent Shared Memory on a Message Passing Machine","author":"Bisiani","year":"1988","journal-title":"Carnegie Mellon University, Technical Report CMU-CS-88-204"},{"key":"10.1016\/0165-6074(93)90132-5_BIB7","series-title":"Proceedings of the 13th International Symposium on Computer Architecture","article-title":"Memory Buffering in Multiprocessors","author":"Dubois","year":"1986"},{"issue":"No. 11","key":"10.1016\/0165-6074(93)90132-5_BIB8","doi-asserted-by":"crossref","DOI":"10.1109\/TC.1982.1675925","article-title":"Effects of Cache Coherency in Multiprocessors","volume":"Vol. c-31","author":"Dubois","year":"1982","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/0165-6074(93)90132-5_BIB9","doi-asserted-by":"crossref","DOI":"10.1109\/2.15","article-title":"Synchronization, Coherence and Event Ordering in Multiprocessors","author":"Dubois","year":"1988","journal-title":"Computer"},{"key":"10.1016\/0165-6074(93)90132-5_BIB10","series-title":"Proceedings of the 15th International Symposium on Computer Architecture","article-title":"Characterization of Sharing in Parallel Programs and its Applicability to Coherency Protocol Evaluation","author":"Eggers","year":"1988"},{"key":"10.1016\/0165-6074(93)90132-5_BIB11","series-title":"Proceedings of the 16th International Symposium on Computer Architecture","article-title":"Evaluating the Performance of four Snooping Cache Coherency Protocols","author":"Eggers","year":"1989"},{"key":"10.1016\/0165-6074(93)90132-5_BIB12","article-title":"SIMON: a Simulator of Multicomputer Networks","author":"Fujimoto","year":"1983"},{"key":"10.1016\/0165-6074(93)90132-5_BIB13","article-title":"SPUR: A VLSI Multiprocessor Workstation","author":"Hill","year":"1986","journal-title":"IEEE Computer"},{"key":"10.1016\/0165-6074(93)90132-5_BIB14","series-title":"Proceedings of the 17th International Symposium on Computer Architecture","article-title":"Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors","author":"Gharachorloo","year":"1990"},{"key":"10.1016\/0165-6074(93)90132-5_BIB15","series-title":"Proceedings of the 10th International Symposium on Computer Architecture","article-title":"Using Cache Memories to Reduce Processor-Memory Traffic","author":"Goodman","year":"1983"},{"key":"10.1016\/0165-6074(93)90132-5_BIB16","doi-asserted-by":"crossref","DOI":"10.1109\/MC.1984.1659188","article-title":"Simulated Performance of a Reduction-Based Multiprocessor","author":"Keller","year":"1984","journal-title":"Computer"},{"issue":"No. 9","key":"10.1016\/0165-6074(93)90132-5_BIB17","doi-asserted-by":"crossref","DOI":"10.1109\/TC.1979.1675439","article-title":"How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs","volume":"Vol. c-28","author":"Lamport","year":"1979","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/0165-6074(93)90132-5_BIB18","series-title":"Proceedings of the 18th International Symposium on Computer Architecture","article-title":"Race-free Interconnection Networks and Multiprocessor Consistency","author":"Landin","year":"1991"},{"key":"10.1016\/0165-6074(93)90132-5_BIB19","series-title":"Cache and Interconnect Architectures in Multiprocessors","article-title":"CHESS Multiprocessor A Processor-Memory Grid for Parallel Programming","author":"Lioupis","year":"1990"},{"key":"10.1016\/0165-6074(93)90132-5_BIB20","series-title":"Proceedings of the 11th International Symposium on Computer Architecture","article-title":"A low-overhead Coherence Solution for Multiprocessors with Private Cache Memories","author":"Papamarcos","year":"1984"},{"key":"10.1016\/0165-6074(93)90132-5_BIB21","article-title":"Encore Eyes Multiprocessor Market","author":"Rose","year":"1985","journal-title":"Electronics"},{"key":"10.1016\/0165-6074(93)90132-5_BIB22","series-title":"Proceedings of the 11th International Symposium on Computer Architecture","article-title":"Dynamic Decentralized Cache Schemes for MIMD Parallel Processors","author":"Rudolph","year":"1984"},{"key":"10.1016\/0165-6074(93)90132-5_BIB23","series-title":"Proceedings of the 14th International Symposium on Computer Architecture","article-title":"Correct Memory Operation of Cache-Based Multiprocessors","author":"Scheurich","year":"1987"},{"key":"10.1016\/0165-6074(93)90132-5_BIB24","series-title":"Balance 8000 Technical Summary","author":"Sequent Computer Systems Inc","year":"1984"},{"key":"10.1016\/0165-6074(93)90132-5_BIB25","series-title":"2nd International Conference on Architectural Support for Programming Languages and Operating Systems","article-title":"Firefly: A Multiprocessor Workstation","author":"Thaker","year":"1987"},{"key":"10.1016\/0165-6074(93)90132-5_BIB26","series-title":"Proceedings of the 15th International Symposium on Computer Architecture","article-title":"An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols","author":"Vernon","year":"1988"},{"key":"10.1016\/0165-6074(93)90132-5_BIB27","series-title":"Proceedings of the 14th International Symposium on Computer Architecture","article-title":"Hierarchical Cache\/Bus Architecture for Shared Memory Multiprocessors","author":"Wilson","year":"1987"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607493901325?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607493901325?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T10:25:22Z","timestamp":1551090322000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607493901325"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,9]]},"references-count":27,"journal-issue":{"issue":"1-5","published-print":{"date-parts":[[1993,9]]}},"alternative-id":["0165607493901325"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(93)90132-5","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1993,9]]}}}