{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T23:04:01Z","timestamp":1648595041720},"reference-count":7,"publisher":"Elsevier BV","issue":"4","license":[{"start":{"date-parts":[[1993,9,1]],"date-time":"1993-09-01T00:00:00Z","timestamp":746841600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1993,9]]},"DOI":"10.1016\/0165-6074(93)90244-f","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T17:14:48Z","timestamp":1062609288000},"page":"205-213","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting multi-way branches to boost superscalar processor performance"],"prefix":"10.1016","volume":"36","author":[{"given":"Yen-Jen","family":"Oyang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(93)90244-F_BIB1","series-title":"Superscalar Microprocessor Design","author":"Johnson","year":"1991"},{"issue":"12","key":"10.1016\/0165-6074(93)90244-F_BIB2","doi-asserted-by":"crossref","DOI":"10.1109\/12.40844","article-title":"The nonuniform distribution of instruction-level and machine parallelism and its effect on performance","volume":"38","author":"Jouppi","year":"1989","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/0165-6074(93)90244-F_BIB3","series-title":"Proc. 3rd Internat. Conf. on Architectural Support for Programming Languages and Operating System","article-title":"Limits on multiple instruction issue","author":"Smith","year":"1989"},{"key":"10.1016\/0165-6074(93)90244-F_BIB4","series-title":"Proc. 18th Annual Internat. Symp. on Computer Architecture","article-title":"IMPACT: An architectural framework for multiple-instruction-issue processors","author":"Chang","year":"1991"},{"key":"10.1016\/0165-6074(93)90244-F_BIB5","series-title":"Proc. 5th Internat. Conf. on Architectural Support for Programming Languages and Operating Systems","article-title":"Efficient superscalar performance through boosting","author":"Smith","year":"1992"},{"key":"10.1016\/0165-6074(93)90244-F_BIB6","doi-asserted-by":"crossref","DOI":"10.1146\/annurev.cs.04.060190.001133","article-title":"Instruction scheduling for superscalar architectures","author":"Lam","year":"1990","journal-title":"Ann. Rev. Comput. Sci."},{"key":"10.1016\/0165-6074(93)90244-F_BIB7","author":"Sun Microsystems Inc.","year":"1987"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749390244F?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749390244F?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T10:22:16Z","timestamp":1551090136000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016560749390244F"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,9]]},"references-count":7,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1993,9]]}},"alternative-id":["016560749390244F"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(93)90244-f","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1993,9]]}}}