{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T17:05:14Z","timestamp":1648659914276},"reference-count":24,"publisher":"Elsevier BV","issue":"6","license":[{"start":{"date-parts":[[1994,7,1]],"date-time":"1994-07-01T00:00:00Z","timestamp":773020800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1994,7]]},"DOI":"10.1016\/0165-6074(94)90105-8","type":"journal-article","created":{"date-parts":[[2003,8,8]],"date-time":"2003-08-08T04:56:10Z","timestamp":1060318570000},"page":"387-410","source":"Crossref","is-referenced-by-count":0,"title":["The architecture of response-pipelined content addressable memories"],"prefix":"10.1016","volume":"40","author":[{"given":"Kanad","family":"Ghose","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(94)90105-8_BIB1","series-title":"AM99C10 256 \u00d7 48 content addressable memory","year":"1989"},{"issue":"1","key":"10.1016\/0165-6074(94)90105-8_BIB2","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/4.16298","article-title":"A pipelined associative memory implemented in VLSI","volume":"24","author":"Clark","year":"1989","journal-title":"IEEE J. Solid State Circuits"},{"key":"10.1016\/0165-6074(94)90105-8_BIB3","article-title":"CMOS implementation of response pipelined CAM chips","author":"Dharmaraj","year":"1992","journal-title":"Master's Thesis, Department of Electrical Engg., SUNY-Binghamton"},{"key":"10.1016\/0165-6074(94)90105-8_BIB4","series-title":"Content Addressable Parallel Processors","author":"Foster","year":"1976"},{"key":"10.1016\/0165-6074(94)90105-8_BIB5","series-title":"Proc. IEEE\/ACM 5th Int. Conf. on VLSI Design","first-page":"161","article-title":"Scalable, pipelined, CMOS VLSI content addressable memory chips","author":"Ghose","year":"1992"},{"key":"10.1016\/0165-6074(94)90105-8_BIB6","series-title":"PNC1480 64Kbit content addressable memory-advance data sheet","year":"1991"},{"issue":"4","key":"10.1016\/0165-6074(94)90105-8_BIB7","doi-asserted-by":"crossref","first-page":"509","DOI":"10.1109\/PGEC.1966.264358","article-title":"Content addressable and associative memory systems, a survey","volume":"EC-15","author":"Hanlon","year":"1966","journal-title":"IEEE Trans. Electronic Comput."},{"key":"10.1016\/0165-6074(94)90105-8_BIB8","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1109\/40.207089","article-title":"A 16-Kbit \u0398-search associative memory","author":"Hurson","year":"1993","journal-title":"IEEE Micro"},{"key":"10.1016\/0165-6074(94)90105-8_BIB9","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1016\/0743-7315(89)90043-9","article-title":"A reconfigurable fully parallel associative processor","volume":"6","author":"Ilgen","year":"1989","journal-title":"J. Parallel Distributed Comput."},{"key":"10.1016\/0165-6074(94)90105-8_BIB10","first-page":"165","article-title":"Design, selection and implementation of a content addressable memory for a VLSI CMOS chip architecture","volume":"135","author":"Jones","year":"1988"},{"issue":"5","key":"10.1016\/0165-6074(94)90105-8_BIB11","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1145\/65755.65761","article-title":"VLSI rule based systems","volume":"16","author":"Kogge","year":"1988","journal-title":"Comput. Architecture News"},{"key":"10.1016\/0165-6074(94)90105-8_BIB12","series-title":"Content Addressable Memories","author":"Kohonen","year":"1987"},{"issue":"2","key":"10.1016\/0165-6074(94)90105-8_BIB13","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1109\/JSSC.1970.1050115","article-title":"Integrated-circuit content-addressable memories","volume":"SC-5","author":"Koo","year":"1970","journal-title":"IEEE J. Solid State Circuits"},{"key":"10.1016\/0165-6074(94)90105-8_BIB14","first-page":"924","article-title":"A content addressable distributed logic memory with applications to information retrieval","volume":"51","author":"Lee","year":"1963"},{"issue":"3","key":"10.1016\/0165-6074(94)90105-8_BIB15","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/40.141603","article-title":"Cascading content addressable memories","volume":"12","author":"Moors","year":"1992","journal-title":"IEEE Micro"},{"issue":"4","key":"10.1016\/0165-6074(94)90105-8_BIB16","doi-asserted-by":"crossref","first-page":"1014","DOI":"10.1109\/4.34086","article-title":"A 20-kbit associative memory LSI for artificial intelligence machines","volume":"24","author":"Ogura","year":"1989","journal-title":"IEEE J. Solid State Circuits"},{"key":"10.1016\/0165-6074(94)90105-8_BIB17","first-page":"722","article-title":"Associative memories and processors: An overview and selected bibliography","volume":"6","author":"Parhami","year":"1973"},{"key":"10.1016\/0165-6074(94)90105-8_BIB18","series-title":"Proc. Int. Conf. on Parallel Processing","first-page":"545","article-title":"Systolic associative memories","author":"Parhami","year":"1990"},{"issue":"9","key":"10.1016\/0165-6074(94)90105-8_BIB19","doi-asserted-by":"crossref","first-page":"800","DOI":"10.1109\/TC.1978.1675200","article-title":"A design of a fast cellular associative memory for ordered retrieval","volume":"C-27","author":"Ramamoorthy","year":"1978","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"10.1016\/0165-6074(94)90105-8_BIB20","first-page":"119","article-title":"Dynamic cross coupled bitline content addressable memory cell for high density arrays","volume":"SC-22","author":"Sodini","year":"1987","journal-title":"IEEE J. Solid State Circuits"},{"key":"10.1016\/0165-6074(94)90105-8_BIB21","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/40.180249","article-title":"A general-purpose CMOS associative processor IC and system","author":"Stormon","year":"1992","journal-title":"IEEE Micro Mag."},{"key":"10.1016\/0165-6074(94)90105-8_BIB22","series-title":"Proc. 5th Conf. on Logic Programming","first-page":"1448","article-title":"An architecture based on content-addressable memory for the rapid execution of Prolog","author":"Stormon","year":"1988"},{"key":"10.1016\/0165-6074(94)90105-8_BIB23","series-title":"Cache memory management data book","year":"1990"},{"issue":"4","key":"10.1016\/0165-6074(94)90105-8_BIB24","doi-asserted-by":"crossref","first-page":"1003","DOI":"10.1109\/4.34085","article-title":"A ternary content addressable search engine","volume":"24","author":"Wade","year":"1989","journal-title":"IEEE J. Solid State Circuits"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607494901058?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607494901058?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,15]],"date-time":"2019-03-15T01:53:41Z","timestamp":1552614821000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607494901058"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,7]]},"references-count":24,"journal-issue":{"issue":"6","published-print":{"date-parts":[[1994,7]]}},"alternative-id":["0165607494901058"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(94)90105-8","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1994,7]]}}}