{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T14:59:24Z","timestamp":1649084364686},"reference-count":14,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1995,6,1]],"date-time":"1995-06-01T00:00:00Z","timestamp":801964800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1995,6]]},"DOI":"10.1016\/0165-6074(95)00009-d","type":"journal-article","created":{"date-parts":[[2003,10,24]],"date-time":"2003-10-24T05:50:20Z","timestamp":1066974620000},"page":"211-225","source":"Crossref","is-referenced-by-count":0,"title":["The multi-associative branch target buffer: a cost effective BTB mechanism"],"prefix":"10.1016","volume":"41","author":[{"given":"Weili","family":"Chu","sequence":"first","affiliation":[]},{"given":"Stamatis","family":"Vassiliadis","sequence":"additional","affiliation":[]},{"given":"Jos\u00e9G.","family":"Delgado-Frias","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"1","key":"10.1016\/0165-6074(95)00009-D_BIB1","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1109\/MC.1984.1658927","article-title":"Branch prediction strategies and branch target buffer design","volume":"17","author":"Lee","year":"1984","journal-title":"Computer"},{"key":"10.1016\/0165-6074(95)00009-D_BIB2","series-title":"Proc. Eighth Symp. Computer Architecture","first-page":"135","article-title":"A study of branch prediction strategies","author":"Smith","year":"1981"},{"key":"10.1016\/0165-6074(95)00009-D_BIB3","author":"Kane","year":"1987"},{"key":"10.1016\/0165-6074(95)00009-D_BIB4","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1147\/rd.341.0023","article-title":"IBM RISC system\/6000 processor architecture","volume":"34","author":"Oehler","year":"1990","journal-title":"IBM J. Research and Development"},{"key":"10.1016\/0165-6074(95)00009-D_BIB5","first-page":"114","article-title":"Optimizing delayed branches","volume":"15","author":"Gross","year":"1982"},{"key":"10.1016\/0165-6074(95)00009-D_BIB6","first-page":"1","article-title":"A branch instruction processor for SCISM architectures","author":"Blaner","year":"1992"},{"key":"10.1016\/0165-6074(95)00009-D_BIB7","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/2.68","article-title":"Reducing the branch penalty in the pipelined processors","volume":"21","author":"Lilja","year":"1988","journal-title":"Computer"},{"issue":"6","key":"10.1016\/0165-6074(95)00009-D_BIB8","doi-asserted-by":"crossref","first-page":"887","DOI":"10.1080\/00207218908925443","article-title":"Condition code predictor for fixed-point arithmetic units","volume":"66","author":"Vassiliadis","year":"1989","journal-title":"Int. J. Electronics"},{"issue":"2","key":"10.1016\/0165-6074(95)00009-D_BIB9","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1080\/00207218908925372","article-title":"Resolution of branching with prediction","volume":"66","author":"Putrino","year":"1989","journal-title":"Int. J. Electronics"},{"issue":"7","key":"10.1016\/0165-6074(95)00009-D_BIB10","doi-asserted-by":"crossref","first-page":"825","DOI":"10.1109\/12.237723","article-title":"Interlock collapsing ALUs","volume":"42","author":"Vassiliadis","year":"1993","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"10.1016\/0165-6074(95)00009-D_BIB11","doi-asserted-by":"crossref","first-page":"121","DOI":"10.1109\/TSE.1978.231482","article-title":"A comparative study of set associative memory mapping algorithms and their use for cache and main memory","volume":"SE-4","author":"Smith","year":"1978","journal-title":"IEEE Trans. Software Eng."},{"issue":"3","key":"10.1016\/0165-6074(95)00009-D_BIB12","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1145\/356887.356892","article-title":"Cache memories","volume":"14","author":"Smith","year":"1982","journal-title":"Comput. Surveys"},{"issue":"3","key":"10.1016\/0165-6074(95)00009-D_BIB13","doi-asserted-by":"crossref","first-page":"265","DOI":"10.1093\/comjnl\/18.3.265","article-title":"Hashing function","volume":"18","author":"Knott","year":"1975","journal-title":"Computer J."},{"issue":"4","key":"10.1016\/0165-6074(95)00009-D_BIB14","doi-asserted-by":"crossref","first-page":"228","DOI":"10.1145\/362575.362578","article-title":"Key-to-address transform techniques: A fundamental performance study on large existing formatted files","author":"Lum","year":"1971","journal-title":"Commun. ACM"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749500009D?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016560749500009D?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,19]],"date-time":"2019-02-19T08:28:28Z","timestamp":1550564908000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016560749500009D"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,6]]},"references-count":14,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1995,6]]}},"alternative-id":["016560749500009D"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(95)00009-d","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1995,6]]}}}