{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,8,26]],"date-time":"2023-08-26T11:42:24Z","timestamp":1693050144986},"reference-count":21,"publisher":"Elsevier BV","issue":"5-6","license":[{"start":{"date-parts":[[1995,10,1]],"date-time":"1995-10-01T00:00:00Z","timestamp":812505600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessing and Microprogramming"],"published-print":{"date-parts":[[1995,10]]},"DOI":"10.1016\/0165-6074(95)99030-9","type":"journal-article","created":{"date-parts":[[2003,10,24]],"date-time":"2003-10-24T05:50:20Z","timestamp":1066974620000},"page":"409-423","source":"Crossref","is-referenced-by-count":6,"title":["Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures"],"prefix":"10.1016","volume":"41","author":[{"given":"E.","family":"De Greef","sequence":"first","affiliation":[]},{"given":"F.","family":"Catthoor","sequence":"additional","affiliation":[]},{"given":"H.","family":"De Man","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0165-6074(95)99030-9_BIB1","series-title":"Proceedings of the 5th IEEE International Workshop on Rapid System Prototyping","first-page":"108","article-title":"Buffer Memory Requirements in DSP Applications","author":"Ad\u00e9","year":"1994"},{"key":"10.1016\/0165-6074(95)99030-9_BIB2","series-title":"Proceedings of Darthmouth Advanced Graduate Studies Symposium on Parallel Computing (DAGS\/PC)","first-page":"162","article-title":"Load Redistribution Algorithms for Parallel Implementations of Intermediate Level Vision Tasks","author":"Argyros","year":"1992"},{"key":"10.1016\/0165-6074(95)99030-9_BIB3","series-title":"Fourth International Workshop","article-title":"Languages and Compilers for Parallel Computing","year":"1991"},{"key":"10.1016\/0165-6074(95)99030-9_BIB4","series-title":"International Conference on Parallel Processing","first-page":"851","article-title":"Load Balancing Protocols on a Local Computer System with a Multiaccess Network","author":"Baumgartner","year":"1987"},{"key":"10.1016\/0165-6074(95)99030-9_BIB5","series-title":"Environments and Tools for Parallel Scientific Computing","article-title":"Loop nest scheduling and transformations","author":"Darte","year":"1993"},{"key":"10.1016\/0165-6074(95)99030-9_BIB6","doi-asserted-by":"crossref","first-page":"1309","DOI":"10.1109\/31.44347","article-title":"Parameterizable VLSI Architectures for the full-search block-matching algorithm","volume":"Vol. 36","author":"De Vos","year":"1989","journal-title":"IEEE Transactions on Circuits and Systems"},{"issue":"no. 2","key":"10.1016\/0165-6074(95)99030-9_BIB7","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1109\/2.15","article-title":"Synchronization, Coherence, and Event Ordering in Multiprocessors","volume":"Vol. 21","author":"Dubois","year":"1988","journal-title":"IEEE Computer"},{"key":"10.1016\/0165-6074(95)99030-9_BIB8","doi-asserted-by":"crossref","first-page":"171","DOI":"10.1007\/BF01581294","article-title":"Design of a processing board for a programmable multi-VSP system","volume":"Vol. 5","author":"Engels","year":"1993","journal-title":"Special Issue of Journal of VLSI Signal Processing"},{"key":"10.1016\/0165-6074(95)99030-9_BIB9","first-page":"254","article-title":"A 250 MHz 16b 1-million transistor BiCMOS super-high-speed video signal processor","author":"Goto","year":"1991","journal-title":"IEEE ISSCC91"},{"issue":"no. 6","key":"10.1016\/0165-6074(95)99030-9_BIB10","doi-asserted-by":"crossref","DOI":"10.1109\/78.218149","article-title":"Scheduling of DSP programs onto multiprocessors for maximum throughput","volume":"Vol. 41","author":"Hoang","year":"1993","journal-title":"IEEE Transactions on Signal Processing"},{"key":"10.1016\/0165-6074(95)99030-9_BIB11","doi-asserted-by":"crossref","first-page":"889","DOI":"10.1109\/78.193224","article-title":"An efficient and simple VLSI tree archjitecture for motion estimation algorithms","volume":"Vol. 41","author":"Jehng","year":"1993","journal-title":"IEEE Transactions on Signal Processing"},{"key":"10.1016\/0165-6074(95)99030-9_BIB12","doi-asserted-by":"crossref","DOI":"10.1109\/31.44346","article-title":"Array Architectures for Block Matching Algorithms","volume":"Vol. 36","author":"Komarek","year":"1989","journal-title":"IEEE Transactions on Circuits and Systems"},{"issue":"no. 12","key":"10.1016\/0165-6074(95)99030-9_BIB13","doi-asserted-by":"crossref","DOI":"10.1109\/29.61542","article-title":"Task Allocation and scheduling models for multiprocessor digital signal processing","volume":"Vol. 38","author":"Konstantinides","year":"1990","journal-title":"IEEE Transactions on Acoustics, Speech and Signal Processing"},{"key":"10.1016\/0165-6074(95)99030-9_BIB14","series-title":"TMS320C80 Multimedia Video Processor (MVP), Technical brief","year":"1994"},{"key":"10.1016\/0165-6074(95)99030-9_BIB15","unstructured":"TMS320C8x MVP, Online reference CD-ROM, release 1.0, Texas Instruments, 1994."},{"key":"10.1016\/0165-6074(95)99030-9_BIB16","series-title":"ISSCC90","first-page":"122","article-title":"A 200 MIPS image signal multiprocessor on a single chip","author":"Maruyama","year":"1990"},{"issue":"no. 12","key":"10.1016\/0165-6074(95)99030-9_BIB17","article-title":"A 300-MOPS video signal processor with a parallel architecture","volume":"Vol. 26","author":"Minami","year":"1991","journal-title":"IEEE JSSC"},{"key":"10.1016\/0165-6074(95)99030-9_BIB18","series-title":"Algorithms and parallel VLSI architectures II","year":"1992"},{"key":"10.1016\/0165-6074(95)99030-9_BIB19","article-title":"Mapping vision algorithms to parallel architectures","volume":"Vol. 76","author":"Stout","year":"1988"},{"key":"10.1016\/0165-6074(95)99030-9_BIB20","doi-asserted-by":"crossref","first-page":"249","DOI":"10.1109\/30.44278","article-title":"A general-purpose programmable video signal processor","author":"van Roermond","year":"1989","journal-title":"IEEE Transactions on Consumer Electronics"},{"key":"10.1016\/0165-6074(95)99030-9_BIB21","doi-asserted-by":"crossref","first-page":"1317","DOI":"10.1109\/31.44348","article-title":"A Family of VLSI designs for the motion compensation block-matching algorithm","volume":"Vol. 36","author":"Yang","year":"1989","journal-title":"IEEE Transactions on Circuits and Systems"}],"container-title":["Microprocessing and Microprogramming"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607495990309?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0165607495990309?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,19]],"date-time":"2019-02-19T08:28:31Z","timestamp":1550564911000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0165607495990309"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,10]]},"references-count":21,"journal-issue":{"issue":"5-6","published-print":{"date-parts":[[1995,10]]}},"alternative-id":["0165607495990309"],"URL":"https:\/\/doi.org\/10.1016\/0165-6074(95)99030-9","relation":{},"ISSN":["0165-6074"],"issn-type":[{"value":"0165-6074","type":"print"}],"subject":[],"published":{"date-parts":[[1995,10]]}}}