{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,3]],"date-time":"2025-11-03T07:27:48Z","timestamp":1762154868820,"version":"build-2065373602"},"reference-count":41,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1993,9,1]],"date-time":"1993-09-01T00:00:00Z","timestamp":746841600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1993,9,1]],"date-time":"1993-09-01T00:00:00Z","timestamp":746841600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Future Generation Computer Systems"],"published-print":{"date-parts":[[1993,9]]},"DOI":"10.1016\/0167-739x(93)90013-f","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T11:12:00Z","timestamp":1062587520000},"page":"219-234","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":1,"title":["A data cache for Prolog architectures"],"prefix":"10.1016","volume":"9","author":[{"given":"Lanfranco","family":"Lopriore","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"year":"1989","author":"Agarwal","series-title":"Analysis of Cache Performance for Operating Systems and Multiprogramming","key":"10.1016\/0167-739X(93)90013-F_BIB1"},{"key":"10.1016\/0167-739X(93)90013-F_BIB2","series-title":"Logic Programming","first-page":"83","article-title":"The memory management of Prolog implementations","author":"Bruynooghe","year":"1982"},{"issue":"1","key":"10.1016\/0167-739X(93)90013-F_BIB3","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/40.16791","article-title":"Implementation studies for a VLSI Prolog coprocessor","volume":"9","author":"Civera","year":"1989","journal-title":"IEEE Micro"},{"year":"1981","author":"Clocksin","series-title":"Programming in Prolog","key":"10.1016\/0167-739X(93)90013-F_BIB4"},{"year":"1987","author":"Conery","series-title":"Parallel Execution of Logic Programs","key":"10.1016\/0167-739X(93)90013-F_BIB5"},{"year":"1990","author":"Dobry","series-title":"A High Performance Architecture for Prolog","key":"10.1016\/0167-739X(93)90013-F_BIB6"},{"key":"10.1016\/0167-739X(93)90013-F_BIB7_1","series-title":"Proc. Thirteenth Annual Internat. Symp. on Computer Architecture","article-title":"On the use of registers vs. cache to minimize memory traffic","author":"Goodman","year":"1986"},{"issue":"2","key":"10.1016\/0167-739X(93)90013-F_BIB7_2","doi-asserted-by":"crossref","first-page":"375","DOI":"10.1145\/17356.17400","article-title":"On the use of registers vs. cache to minimize memory traffic","volume":"14","author":"Goodman","year":"1986","journal-title":"Computer Architecture News"},{"key":"10.1016\/0167-739X(93)90013-F_BIB8_1","series-title":"Proc. Second Internat. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS II)","article-title":"An architecture for the direct execution of the Forth programming language","author":"Hayes","year":"1987"},{"issue":"5","key":"10.1016\/0167-739X(93)90013-F_BIB8_2","doi-asserted-by":"crossref","DOI":"10.1145\/36177.36182","article-title":"An architecture for the direct execution of the Forth programming language","volume":"15","author":"Hayes","year":"1987","journal-title":"Computer Architecture News"},{"issue":"4","key":"10.1016\/0167-739X(93)90013-F_BIB8_3","article-title":"An architecture for the direct execution of the Forth programming language","volume":"21","author":"Hayes","year":"1987","journal-title":"Operat. Syst. Rev."},{"issue":"10","key":"10.1016\/0167-739X(93)90013-F_BIB8_4","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1145\/36205.36182","article-title":"An architecture for the direct execution of the Forth programming language","volume":"22","author":"Hayes","year":"1987","journal-title":"SIGPLAN Notices"},{"year":"1990","author":"Hennessy","series-title":"Computer Architecture: A Quantitative Approach","key":"10.1016\/0167-739X(93)90013-F_BIB9"},{"year":"1984","author":"Hogger","series-title":"Introduction to Logic Programming","key":"10.1016\/0167-739X(93)90013-F_BIB10"},{"year":"1992","author":"Kane","series-title":"MIPS RISC Architecture","key":"10.1016\/0167-739X(93)90013-F_BIB11"},{"key":"10.1016\/0167-739X(93)90013-F_BIB12","series-title":"Proc. Eighteenth Annual Internat. Symp. on Computer Architecture","first-page":"43","article-title":"An architecture for software-controlled data prefetching","author":"Klaiber","year":"1991"},{"year":"1980","author":"Kohonen","series-title":"Content-Addressable Memories","key":"10.1016\/0167-739X(93)90013-F_BIB13"},{"key":"10.1016\/0167-739X(93)90013-F_BIB14","first-page":"1538","article-title":"Virtual address cache with no reverse address buffering","volume":"76","author":"Lopriore","year":"1988"},{"issue":"3","key":"10.1016\/0167-739X(93)90013-F_BIB15","doi-asserted-by":"crossref","first-page":"125","DOI":"10.1016\/0020-0190(89)90190-7","article-title":"Software-controlled cache coherence protocol for multicache systems","volume":"33","author":"Lopriore","year":"1989","journal-title":"Informat. Processing Letters"},{"year":"1982","author":"Madison","series-title":"Characteristics of Program Localities","key":"10.1016\/0167-739X(93)90013-F_BIB16"},{"issue":"3","key":"10.1016\/0167-739X(93)90013-F_BIB17","doi-asserted-by":"crossref","first-page":"230","DOI":"10.1145\/99926.99933","article-title":"The effect of processor architecture on instruction memory traffic","volume":"8","author":"Mitchell","year":"1990","journal-title":"ACM Trans. Comput. Syst."},{"key":"10.1016\/0167-739X(93)90013-F_BIB18_1","series-title":"Proc. 16th Annual Internat. Symp. on Computer Architecture","article-title":"Evaluation of memory system for integrated Prolog processor IPP","author":"Morioka","year":"1989"},{"issue":"3","key":"10.1016\/0167-739X(93)90013-F_BIB18_2","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1145\/74926.74949","article-title":"Evaluation of memory system for integrated Prolog processor IPP","volume":"17","author":"Morioka","year":"1989","journal-title":"Comput. Architecture News"},{"key":"10.1016\/0167-739X(93)90013-F_BIB19","first-page":"1605","article-title":"Microprocessor technology trends","volume":"74","author":"Myers","year":"1986"},{"key":"10.1016\/0167-739X(93)90013-F_BIB20_1","series-title":"Proc. Fourth Annual Symp. on Computer Architecture","article-title":"An instruction timing model of CPU performance","author":"Peuto","year":"1977"},{"issue":"7","key":"10.1016\/0167-739X(93)90013-F_BIB20_2","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1145\/633615.810667","article-title":"An instruction timing model of CPU performance","volume":"5","author":"Peuto","year":"1977","journal-title":"Comput. Architecture News"},{"year":"1983","author":"Pohm","series-title":"High-Speed Memory Systems","key":"10.1016\/0167-739X(93)90013-F_BIB21"},{"issue":"2","key":"10.1016\/0167-739X(93)90013-F_BIB22","doi-asserted-by":"crossref","first-page":"121","DOI":"10.1109\/TSE.1978.231482","article-title":"A comparative study of set associative memory mapping algorithms and their use for cache and main memory","author":"Smith","year":"1978","journal-title":"IEEE Trans. Software Engrg. SE-4"},{"issue":"1","key":"10.1016\/0167-739X(93)90013-F_BIB23","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1145\/322108.322110","article-title":"Characterizing the storage process and its effect on the update of main memory by write through","volume":"26","author":"Smith","year":"1979","journal-title":"JACM"},{"issue":"3","key":"10.1016\/0167-739X(93)90013-F_BIB24","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1145\/356887.356892","article-title":"Cache memories","volume":"14","author":"Smith","year":"1982","journal-title":"Computing Surveys"},{"key":"10.1016\/0167-739X(93)90013-F_BIB25_1","series-title":"Proc. Twelfth Annual Internat. Symp. on Computer Architecture","article-title":"Cache evaluation and the impact of workload choice","author":"Smith","year":"1985"},{"issue":"3","key":"10.1016\/0167-739X(93)90013-F_BIB25_2","doi-asserted-by":"crossref","first-page":"64","DOI":"10.1145\/327070.327132","article-title":"Cache evaluation and the impact of workload choice","volume":"13","author":"Smith","year":"1985","journal-title":"SIGARCH Newsletter"},{"issue":"9","key":"10.1016\/0167-739X(93)90013-F_BIB26","doi-asserted-by":"crossref","first-page":"1063","DOI":"10.1109\/TC.1987.5009537","article-title":"Line (block) size choice for CPU cache memories","author":"Smith","year":"1987","journal-title":"IEEE Trans. Comput. C-36"},{"issue":"3","key":"10.1016\/0167-739X(93)90013-F_BIB27","doi-asserted-by":"crossref","first-page":"234","DOI":"10.1109\/TC.1985.1676566","article-title":"Instruction cache replacement policies and organizations","author":"Smith","year":"1985","journal-title":"IEEE Trans. Comput. C-34"},{"issue":"6","key":"10.1016\/0167-739X(93)90013-F_BIB28","doi-asserted-by":"crossref","first-page":"700","DOI":"10.1109\/12.2208","article-title":"Cache operations by MRU change","volume":"37","author":"So","year":"1988","journal-title":"IEEE Trans. Comput."},{"year":"1987","author":"Stone","series-title":"High-Performance Computer Architecture","key":"10.1016\/0167-739X(93)90013-F_BIB29"},{"key":"10.1016\/0167-739X(93)90013-F_BIB30_1","series-title":"Proc. Third Internat. Conf. on Logic Programming","article-title":"Memory performance of Lisp and Prolog programs","author":"Tick","year":"1986"},{"key":"10.1016\/0167-739X(93)90013-F_BIB30_2","doi-asserted-by":"crossref","first-page":"642","DOI":"10.1007\/3-540-16492-8_113","article-title":"Memory performance of Lisp and Prolog programs","volume":"225","author":"Tick","year":"1986","journal-title":"Lecture Notes in Computer Science"},{"year":"1988","author":"Tick","series-title":"Memory Performance of Prolog Architectures","key":"10.1016\/0167-739X(93)90013-F_BIB31"},{"year":"1989","author":"van de Goor","series-title":"Computer Architecture and Design","key":"10.1016\/0167-739X(93)90013-F_BIB32"},{"year":"1977","author":"Warren","article-title":"Implementing Prolog \u2014 Compiling predicate logic programs","key":"10.1016\/0167-739X(93)90013-F_BIB33"}],"container-title":["Future Generation Computer Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167739X9390013F?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167739X9390013F?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,11,3]],"date-time":"2025-11-03T07:21:38Z","timestamp":1762154498000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0167739X9390013F"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,9]]},"references-count":41,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1993,9]]}},"alternative-id":["0167739X9390013F"],"URL":"https:\/\/doi.org\/10.1016\/0167-739x(93)90013-f","relation":{},"ISSN":["0167-739X"],"issn-type":[{"type":"print","value":"0167-739X"}],"subject":[],"published":{"date-parts":[[1993,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A data cache for Prolog architectures","name":"articletitle","label":"Article Title"},{"value":"Future Generation Computer Systems","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-739X(93)90013-F","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1993 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}