{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T12:02:57Z","timestamp":1648728177540},"reference-count":17,"publisher":"Elsevier BV","issue":"1","license":[{"start":{"date-parts":[[1994,4,1]],"date-time":"1994-04-01T00:00:00Z","timestamp":765158400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Future Generation Computer Systems"],"published-print":{"date-parts":[[1994,4]]},"DOI":"10.1016\/0167-739x(94)90049-3","type":"journal-article","created":{"date-parts":[[2003,9,3]],"date-time":"2003-09-03T15:12:00Z","timestamp":1062601920000},"page":"29-43","source":"Crossref","is-referenced-by-count":0,"title":["Architecture of parallel management kernel for PIE64"],"prefix":"10.1016","volume":"10","author":[{"given":"Yasuo","family":"Hidaka","sequence":"first","affiliation":[]},{"given":"Hanpei","family":"Koike","sequence":"additional","affiliation":[]},{"given":"Hidehiko","family":"Tanaka","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0167-739X(94)90049-3_BIB1","series-title":"Proc. 1992 Int. Workshop on Memory Management","first-page":"43","article-title":"Collection schemes for distributed garbage","author":"Abdullahi","year":"1992"},{"key":"10.1016\/0167-739X(94)90049-3_BIB2","article-title":"Two fundamental issues in multiprocessing","author":"Arvind","year":"1987"},{"issue":"2","key":"10.1016\/0167-739X(94)90049-3_BIB3","doi-asserted-by":"crossref","first-page":"141","DOI":"10.1109\/32.4634","article-title":"A taxonomy of scheduling in general-purpose distributed computing systems","author":"Casavant","year":"1988","journal-title":"IEEE Trans. Software Eng."},{"key":"10.1016\/0167-739X(94)90049-3_BIB4","series-title":"Parallel Logic Programming in Parlog: The Language and its implementation","author":"Gregory","year":"1987"},{"key":"10.1016\/0167-739X(94)90049-3_BIB5","first-page":"37","article-title":"The architecture of the inference unit of Parallel Inference Engine PIE64","author":"Hidaka","year":"1990"},{"key":"10.1016\/0167-739X(94)90049-3_BIB6","series-title":"Proc. 1991 Int. Symp. on Logic Programming","first-page":"470","article-title":"A static load partitioning method based on execution profile for committed choice languages","author":"Hidaka","year":"1991"},{"key":"10.1016\/0167-739X(94)90049-3_BIB7","first-page":"63","article-title":"Overview of the Parallel Inference Engine: PIE64","volume":"Vol. 48","author":"Koike","year":"1990"},{"key":"10.1016\/0167-739X(94)90049-3_BIB8","series-title":"Proc. High Performance and Parallel Lisp Workshop","article-title":"Generation scavenging GC on distributed-memory parallel computers","author":"Koike","year":"1990"},{"key":"10.1016\/0167-739X(94)90049-3_BIB9","series-title":"Proc. Int. Conf. on Fifth Generation Computer Systems","first-page":"1031","article-title":"Massively parallel implementation of Flat GHC on the Connection Machine","author":"Nilsson","year":"1988"},{"key":"10.1016\/0167-739X(94)90049-3_BIB10","series-title":"Proc. Int. Conf. on Fifth Generation Computer Systems","first-page":"458","article-title":"Systolic programming: A paradigm of parallel processing","author":"Shapiro","year":"1984"},{"key":"10.1016\/0167-739X(94)90049-3_BIB11","volume":"Vols. 1, 2","year":"1987"},{"key":"10.1016\/0167-739X(94)90049-3_BIB12","series-title":"Proc. Int. Conf. on Fifth Generation Computer Systems","first-page":"715","article-title":"UNIRED II: The high performance inference processor for the Parallel Inference Machine PIE64","author":"Shimada","year":"1992"},{"key":"10.1016\/0167-739X(94)90049-3_BIB13","first-page":"87dash5","article-title":"Details of the network interface processor for PIE64","author":"Shimizu","year":"1991"},{"key":"10.1016\/0167-739X(94)90049-3_BIB14","series-title":"Proc. IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing","first-page":"5","article-title":"A study of a high bandwidth and low latency interconnection network in PIE64","author":"Takahashi","year":"1991"},{"key":"10.1016\/0167-739X(94)90049-3_BIB15","series-title":"Proc. Int. Conf. on Fifth Generation Computer Systems","first-page":"978","article-title":"A load balancing mechanism for large scale multiprocessor systems and its implementation","author":"Takeda","year":"1988"},{"key":"10.1016\/0167-739X(94)90049-3_BIB16","article-title":"Parallel Inference Machine PIM","author":"Taki","year":"1992"},{"key":"10.1016\/0167-739X(94)90049-3_BIB17","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-16479-0_17","article-title":"Guarded Horn Clauses","author":"Ueda","year":"1986"}],"container-title":["Future Generation Computer Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167739X94900493?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167739X94900493?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,25]],"date-time":"2019-02-25T11:54:17Z","timestamp":1551095657000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0167739X94900493"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,4]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1994,4]]}},"alternative-id":["0167739X94900493"],"URL":"https:\/\/doi.org\/10.1016\/0167-739x(94)90049-3","relation":{},"ISSN":["0167-739X"],"issn-type":[{"value":"0167-739X","type":"print"}],"subject":[],"published":{"date-parts":[[1994,4]]}}}