{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T21:30:57Z","timestamp":1757626257071,"version":"3.44.0"},"reference-count":19,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1984,9,1]],"date-time":"1984-09-01T00:00:00Z","timestamp":462844800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1984,9,1]],"date-time":"1984-09-01T00:00:00Z","timestamp":462844800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1984,9]]},"DOI":"10.1016\/0167-9260(84)90041-5","type":"journal-article","created":{"date-parts":[[2004,5,26]],"date-time":"2004-05-26T17:49:12Z","timestamp":1085593752000},"page":"191-211","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":7,"title":["A VLSI model for residue number system architectures"],"prefix":"10.1016","volume":"2","author":[{"given":"M.A.","family":"Bayoumi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.A.","family":"Jullien","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.C.","family":"Miller","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"2","key":"10.1016\/0167-9260(84)90041-5_BIB1","article-title":"LSI's for digital signal processing","volume":"SC\u201314","author":"Ohmada","year":"1979","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/0167-9260(84)90041-5_BIB2_1","first-page":"2","article-title":"Very large scale integrated circuits for digital signal processing","author":"Buie","year":"1977","journal-title":"Circuits and Systems"},{"key":"10.1016\/0167-9260(84)90041-5_BIB2_2","first-page":"2","article-title":"Very large scale integrated circuits for digital signal processing","author":"Buie","year":"1977","journal-title":"Circuits and Systems"},{"key":"10.1016\/0167-9260(84)90041-5_BIB3","series-title":"Proc. 5th Symp. on Computer Architecture","first-page":"139","article-title":"An approach to using VLSI in digital systems","author":"Patil","year":"1978"},{"key":"10.1016\/0167-9260(84)90041-5_BIB4","doi-asserted-by":"crossref","first-page":"191","DOI":"10.1109\/TCS.1977.1084321","article-title":"The use of Residue Number Systems in the design of finite impulse response digital filters","volume":"CAS\u201324","author":"Jenkins","year":"1977","journal-title":"IEEE Trans. Circuits and Systems"},{"key":"10.1016\/0167-9260(84)90041-5_BIB5","first-page":"65","article-title":"A high speed low-cost recursive filter using residue arithmetic","author":"Soderstrand","year":"1977"},{"key":"10.1016\/0167-9260(84)90041-5_BIB6","doi-asserted-by":"crossref","first-page":"325","DOI":"10.1109\/TC.1978.1675105","article-title":"Residue number scaling and other operations using ROM arrays","volume":"C\u201327","author":"Jullien","year":"1978","journal-title":"IEEE Trans. Comput.,"},{"key":"10.1016\/0167-9260(84)90041-5_BIB7","series-title":"11th Ann. ACM Symp. on Theory of Computing","first-page":"81","article-title":"Area-time complexity for VLSI","author":"Thompson","year":"1979"},{"key":"10.1016\/0167-9260(84)90041-5_BIB8","series-title":"12th Ann. ACM Symp. on Theory of Computing","first-page":"190","article-title":"The chip complexity of binary arithmetic","author":"Brent","year":"1980"},{"key":"10.1016\/0167-9260(84)90041-5_BIB9","doi-asserted-by":"crossref","first-page":"533","DOI":"10.1109\/T-ED.1979.19457","article-title":"Cost and performance of VLSI computing structures","volume":"ED\u201326","author":"Mead","year":"1979","journal-title":"IEEE Trans. on Electron Devices"},{"issue":"4","key":"10.1016\/0167-9260(84)90041-5_BIB10","doi-asserted-by":"crossref","first-page":"317","DOI":"10.1016\/S0167-9260(83)80005-4","article-title":"An area-time efficient NMOS adder","volume":"1","author":"Bayoumi","year":"1983","journal-title":"INTEGRATION, The VLSI Journal"},{"key":"10.1016\/0167-9260(84)90041-5_BIB11","series-title":"14th Ann. Pittsburgh Conf. on Modelling and Simulation","article-title":"Modelling of Residue Number System arithmetic chips","author":"Bayoumi","year":"1983"},{"key":"10.1016\/0167-9260(84)90041-5_BIB12","doi-asserted-by":"crossref","first-page":"307","DOI":"10.1109\/T-C.1973.223711","article-title":"Error correcting properties of redundant Residue Number Systems","volume":"C\u201322","author":"Barsi","year":"1973","journal-title":"IEEE Trans. Comput.,"},{"key":"10.1016\/0167-9260(84)90041-5_BIB13","first-page":"321","article-title":"An autoscale residue multiplier","volume":"C\u201331","author":"Taylor","year":"1981","journal-title":"IEEE Trans. Comput.,"},{"year":"1967","series-title":"Residue Arithmetic and Its Applications to Computer Technology","author":"Zabo","key":"10.1016\/0167-9260(84)90041-5_BIB14"},{"year":"1979","series-title":"Introduction to VLSI Systems","author":"Mead","key":"10.1016\/0167-9260(84)90041-5_BIB15"},{"key":"10.1016\/0167-9260(84)90041-5_BIB16","first-page":"542","article-title":"Delay-time optimization for driving and sensing of signals on high-capcitance paths of VLSI systems","volume":"ED\u201326","author":"Mohsen","year":"1979","journal-title":"IEEE Trans. Electron Devices"},{"key":"10.1016\/0167-9260(84)90041-5_BIB17","series-title":"Proc. 2nd Europ. Signal Processing Conf.,","first-page":"837","article-title":"A VLSI implementation of an NNT multiplier using RNS for digital signal processing applications","author":"Bayoumi","year":"1983"},{"key":"10.1016\/0167-9260(84)90041-5_BIB18","series-title":"26th Midwest Symp. on Circuits and Systems","article-title":"RNS modules for VLSI implementation of digital filters","author":"Jullien","year":"1983"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167926084900415?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167926084900415?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T21:38:08Z","timestamp":1757453888000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0167926084900415"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1984,9]]},"references-count":19,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1984,9]]}},"alternative-id":["0167926084900415"],"URL":"https:\/\/doi.org\/10.1016\/0167-9260(84)90041-5","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1984,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A VLSI model for residue number system architectures","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-9260(84)90041-5","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1984 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}