{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T21:31:05Z","timestamp":1757626265840,"version":"3.44.0"},"reference-count":18,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1989,9,1]],"date-time":"1989-09-01T00:00:00Z","timestamp":620611200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1989,9,1]],"date-time":"1989-09-01T00:00:00Z","timestamp":620611200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1989,9]]},"DOI":"10.1016\/0167-9260(89)90002-3","type":"journal-article","created":{"date-parts":[[2003,3,14]],"date-time":"2003-03-14T14:37:33Z","timestamp":1047652653000},"page":"213-230","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":3,"title":["A note on hierarchical layer-assignment"],"prefix":"10.1016","volume":"7","author":[{"given":"Reiner","family":"Kolla","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Molitor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/0167-9260(89)90002-3_BIB1","article-title":"CADIC \u2014 a system for hierarchical design of integrated circuits","author":"Becker","year":"1986","journal-title":"TR-07\/1986, Sonderforschungsbereich 124-B1"},{"key":"10.1016\/0167-9260(89)90002-3_BIB2","series-title":"Proc. 24th Design Automation Conference","first-page":"649","article-title":"Hierarchical design based on a calculus of nets","author":"Becker","year":"1987"},{"key":"10.1016\/0167-9260(89)90002-3_BIB3","series-title":"Proc. CVIM 86","first-page":"130","author":"Butterfield","year":"1986"},{"article-title":"Implementation of algorithmsfor maximum matching on non-bipartite graphs","year":"1973","author":"Gabow","key":"10.1016\/0167-9260(89)90002-3_BIB4"},{"issue":"1,2","key":"10.1016\/0167-9260(89)90002-3_BIB5_1","first-page":"28","article-title":"Ein logisch-topologischer Kalk\u00fcl zur Konstruktion integrieter Schaltkreise","volume":"1","author":"Hotz","year":"1986","journal-title":"Informatik Forschung & Entwicklung"},{"issue":"1,2","key":"10.1016\/0167-9260(89)90002-3_BIB5_2","first-page":"72","article-title":"Ein logisch-topologischer Kalk\u00fcl zur Konstruktion integrierter Schaltkreise","volume":"1","author":"Hotz","year":"1986","journal-title":"Informatik Forschung & Entwicklung"},{"article-title":"Spezification und Expansion logisch topologischer Netze","year":"1986","author":"Kolla","key":"10.1016\/0167-9260(89)90002-3_BIB6"},{"key":"10.1016\/0167-9260(89)90002-3_BIB7","article-title":"Verification of logic topological nets","author":"Kolla","year":"1988","journal-title":"Technical Report, Sonderforschungsbereich 124-B1"},{"key":"10.1016\/0167-9260(89)90002-3_BIB8","article-title":"Hierarchical graph algorithms","author":"Lengauer","year":"1984","journal-title":"TR-15\/1984, Sonderforschungsbereich 124-B2"},{"article-title":"Efficient solution of connectivity problems on hierarchically defined graphs","year":"1987","author":"Lengauer","key":"10.1016\/0167-9260(89)90002-3_BIB9"},{"key":"10.1016\/0167-9260(89)90002-3_BIB10","series-title":"Proc. IFIP Congress","first-page":"155","article-title":"Recursive implementation of optimal time VLSI integer multipliers","author":"Luk","year":"1983"},{"key":"10.1016\/0167-9260(89)90002-3_BIB11","doi-asserted-by":"crossref","first-page":"345","DOI":"10.1016\/0165-6074(85)90027-4","article-title":"Layer assignment by stimulated annealing","volume":"16","author":"Molitor","year":"1985","journal-title":"The EuroMicro J. Microproces and Microprogram"},{"key":"10.1016\/0167-9260(89)90002-3_BIB12","series-title":"Proc. 4th Annual Symposium on Theoretical Aspects of Computer Science (STACS87)","first-page":"420","article-title":"On the contact-minimization-problem","author":"Molitor","year":"1987"},{"article-title":"\u00dcber die Bikategorie der logisch-topologischen Netze und ihre Semantik","year":"1986","author":"Molitor","key":"10.1016\/0167-9260(89)90002-3_BIB13"},{"issue":"3","key":"10.1016\/0167-9260(89)90002-3_BIB14","doi-asserted-by":"crossref","first-page":"117","DOI":"10.3233\/FI-1988-11202","article-title":"Free net algebras in VLSI-theory","volume":"XI","author":"Molitor","year":"1988","journal-title":"Fundamenta Informaticae"},{"key":"10.1016\/0167-9260(89)90002-3_BIB15","first-page":"398","article-title":"Optimal layer assignment for interconnect","author":"Pinter","year":"1982"},{"article-title":"\u03bcFP \u2014 an algebraic VLSI design language","year":"1984","author":"Sheeran","key":"10.1016\/0167-9260(89)90002-3_BIB16"},{"key":"10.1016\/0167-9260(89)90002-3_BIB17","first-page":"226","article-title":"Conditional-sum addition logic","volume":"9","author":"Sklansky","year":"1960","journal-title":"IRE-EC"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167926089900023?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167926089900023?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T21:36:50Z","timestamp":1757453810000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0167926089900023"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,9]]},"references-count":18,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1989,9]]}},"alternative-id":["0167926089900023"],"URL":"https:\/\/doi.org\/10.1016\/0167-9260(89)90002-3","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1989,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A note on hierarchical layer-assignment","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-9260(89)90002-3","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1989 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}