{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T21:32:13Z","timestamp":1757626333697,"version":"3.44.0"},"reference-count":15,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1989,11,1]],"date-time":"1989-11-01T00:00:00Z","timestamp":625881600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1989,11,1]],"date-time":"1989-11-01T00:00:00Z","timestamp":625881600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1989,11]]},"DOI":"10.1016\/0167-9260(89)90047-3","type":"journal-article","created":{"date-parts":[[2003,3,14]],"date-time":"2003-03-14T14:37:33Z","timestamp":1047652653000},"page":"173-187","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":2,"title":["Efficient false path elimination algorithms for timing verification by event graph preprocessing"],"prefix":"10.1016","volume":"8","author":[{"given":"L.","family":"Claesen","sequence":"first","affiliation":[]},{"given":"J.-P.","family":"Schupp","sequence":"additional","affiliation":[]},{"given":"P.","family":"Das","sequence":"additional","affiliation":[]},{"given":"P.","family":"Johannes","sequence":"additional","affiliation":[]},{"given":"S.","family":"Perremans","sequence":"additional","affiliation":[]},{"given":"H.","family":"De Man","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0167-9260(89)90047-3_BIB1","doi-asserted-by":"crossref","DOI":"10.1109\/TCAD.1987.1270345","article-title":"A new approach for statistical and hierarchical timing simulations","author":"Benkoski","year":"1987"},{"key":"10.1016\/0167-9260(89)90047-3_BIB2","first-page":"24","article-title":"Efficient algorithms for solving the false path problem in timing verifiers","author":"Benkoski","year":"1987"},{"issue":"3","key":"10.1016\/0167-9260(89)90047-3_BIB3","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1109\/TCAD.1985.1270126","article-title":"DIALOG, an expert debugging system for MOSVLSI design","volume":"CAD-4","author":"De Man","year":"1985","journal-title":"IEEE Trans. Comput. Aided Des."},{"issue":"1","key":"10.1016\/0167-9260(89)90047-3_BIB4","doi-asserted-by":"crossref","first-page":"100","DOI":"10.1147\/rd.261.0100","article-title":"Timing analysis of computer hardware","volume":"26","author":"Hitchcock","year":"1982","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/0167-9260(89)90047-3_BIB5","first-page":"227","article-title":"An accurate delay modeling technique for switch-level timing verification","author":"Hwang","year":"1986","journal-title":"23rd Des. Autom. Conf."},{"key":"10.1016\/0167-9260(89)90047-3_BIB6","first-page":"72","article-title":"TV: An nMOS timing analyzer","author":"Jouppi","year":"1983"},{"key":"10.1016\/0167-9260(89)90047-3_BIB7","series-title":"Proc. Eur. Solid State Circuits Conf. ESSCIRC\u203286","first-page":"205","article-title":"SLOCOP: A timing verification tool for synchronous CMOS logic","author":"Meersch","year":"1986"},{"key":"10.1016\/0167-9260(89)90047-3_BIB8","series-title":"Proc. 1988 IEEE Int. Symp. Circuits Syst. ISCAS-88","first-page":"487","article-title":"Automated analysis of timing faults in synchronous MOS circuits","author":"Meersch","year":"1988"},{"key":"10.1016\/0167-9260(89)90047-3_BIB9","first-page":"58","article-title":"Crystal: A timing analyzer for nMOS VLSI circuits","author":"Ousterhout","year":"1980"},{"key":"10.1016\/0167-9260(89)90047-3_BIB10","series-title":"Proc. 26th ACM \/ IEEE Des. Autom. Conf. DAC","article-title":"Static timing analysis of dynamically sensitizable paths","author":"Perremans","year":"1989"},{"issue":"3","key":"10.1016\/0167-9260(89)90047-3_BIB11","doi-asserted-by":"crossref","first-page":"533","DOI":"10.1109\/JSSC.1982.1051771","article-title":"A 32-bit execution unit in an advanced NMOS technology","volume":"SC-17","author":"Pomper","year":"1982","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/0167-9260(89)90047-3_BIB12","doi-asserted-by":"crossref","first-page":"278","DOI":"10.1147\/rd.104.0278","article-title":"Diagnosis of automata failures: A calculus and a new method","author":"Roth","year":"1966","journal-title":"IBM J. Res. Dev."},{"article-title":"STIVITS: A high performance timing verification system for VLSI-chips based on compiled code generation","year":"1988","author":"Schupp","key":"10.1016\/0167-9260(89)90047-3_BIB13"},{"key":"10.1016\/0167-9260(89)90047-3_BIB14","series-title":"IEEE ICCAD\u203286","first-page":"130","article-title":"LEADOUT: A static timing analyzer of MOS circuits","author":"Szymanski","year":"1986"},{"key":"10.1016\/0167-9260(89)90047-3_BIB15","first-page":"683","article-title":"Plug-in timing models for an abstract timing verifier","author":"Wallace","year":"1986"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167926089900473?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0167926089900473?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T21:36:59Z","timestamp":1757453819000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0167926089900473"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,11]]},"references-count":15,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1989,11]]}},"alternative-id":["0167926089900473"],"URL":"https:\/\/doi.org\/10.1016\/0167-9260(89)90047-3","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1989,11]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Efficient false path elimination algorithms for timing verification by event graph preprocessing","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-9260(89)90047-3","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1989 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}