{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T21:30:18Z","timestamp":1757626218013,"version":"3.44.0"},"reference-count":14,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1991,4,1]],"date-time":"1991-04-01T00:00:00Z","timestamp":670464000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1991,4,1]],"date-time":"1991-04-01T00:00:00Z","timestamp":670464000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1991,4]]},"DOI":"10.1016\/0167-9260(91)90019-h","type":"journal-article","created":{"date-parts":[[2003,3,14]],"date-time":"2003-03-14T14:37:33Z","timestamp":1047652653000},"page":"191-204","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"title":["An analytic algorithm for global circuit placement"],"prefix":"10.1016","volume":"11","author":[{"given":"Chong-Min","family":"Kyung","sequence":"first","affiliation":[]},{"given":"Peter V.","family":"Kraus","sequence":"additional","affiliation":[]},{"given":"Dieter A.","family":"Mlynski","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0167-9260(91)90019-H_BIB1","first-page":"343","article-title":"Min-cut placement","volume":"1","author":"Breuer","year":"1977","journal-title":"J. Des. Autom. Fault Tolerant Computing"},{"issue":"1","key":"10.1016\/0167-9260(91)90019-H_BIB2","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1109\/TCAD.1985.1270101","article-title":"A procedure for placement of standard-cell VLSI circuits","volume":"CAD-4","author":"Dunlop","year":"1985","journal-title":"IEEE Trans. CAD IC's Syst."},{"key":"10.1016\/0167-9260(91)90019-H_BIB3","doi-asserted-by":"crossref","first-page":"377","DOI":"10.1109\/TCS.1979.1084652","article-title":"A force-directed component placement procedure for printed circuit boards","volume":"CAS-26","author":"Quinn","year":"1979","journal-title":"IEEE Trans. Circuits and System"},{"key":"10.1016\/0167-9260(91)90019-H_BIB4","doi-asserted-by":"crossref","first-page":"416","DOI":"10.1002\/cta.4490160406","article-title":"Module placement for large chips based on sparse linear equations","volume":"16","author":"Tsay","year":"1988","journal-title":"Int. J. Circuit Theory Appl."},{"issue":"7","key":"10.1016\/0167-9260(91)90019-H_BIB5","doi-asserted-by":"crossref","first-page":"218","DOI":"10.1109\/TCAD.1984.1270078","article-title":"Module placement based on resistive network, optimization","volume":"CAD-3","author":"Cheng","year":"1984","journal-title":"IEEE Trans. CAD IC's Systems"},{"key":"10.1016\/0167-9260(91)90019-H_BIB6","series-title":"Proc. ICCAD","first-page":"506","article-title":"GORDIAN: A new global optimization\/rectangle dissection method for cell placement","author":"Kleinhans","year":"1988"},{"key":"10.1016\/0167-9260(91)90019-H_BIB7","series-title":"Proc. 19th DAC","first-page":"671","article-title":"A combined force and cut algorithm for hierarchical VLSI layout","author":"Wipfler","year":"1982"},{"key":"10.1016\/0167-9260(91)90019-H_BIB8","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"Kirkpatrick","year":"1983","journal-title":"Science"},{"key":"10.1016\/0167-9260(91)90019-H_BIB9","first-page":"432","article-title":"Timber-Wolf 3.2: A new standard cell placement and global routing package","volume":"DAC(6)","author":"Sechen","year":"1986"},{"key":"10.1016\/0167-9260(91)90019-H_BIB10","doi-asserted-by":"crossref","first-page":"622","DOI":"10.1002\/cta.4490160405","article-title":"Graphs in floor plan design","volume":"16","author":"Otten","year":"1988","journal-title":"Int. J. Circuit Theory Appl."},{"key":"10.1016\/0167-9260(91)90019-H_BIB11","doi-asserted-by":"crossref","first-page":"477","DOI":"10.1109\/TCAD.1986.1270219","article-title":"MASON: A global floorplanning approach for VLSI design","volume":"CAD-5","author":"La Potin","year":"1986","journal-title":"IEEE Trans. CAD IC's systems"},{"key":"10.1016\/0167-9260(91)90019-H_BIB12","series-title":"Proc. ISCAS","first-page":"921","article-title":"Step by step placement strategies for building block layout","author":"Onodera","year":"1989"},{"key":"10.1016\/0167-9260(91)90019-H_BIB13","series-title":"Proc. IFIP Int. Conf. VLSI","first-page":"423","article-title":"Macrocell placement by global optimization with uniform cell distribution","author":"Ranke","year":"1989"},{"key":"10.1016\/0167-9260(91)90019-H_BIB14","series-title":"Proc. 24th DAC","first-page":"319","article-title":"Benchmarks for cell-based layout systems","author":"Preas","year":"1987"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016792609190019H?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016792609190019H?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T21:37:20Z","timestamp":1757453840000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016792609190019H"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,4]]},"references-count":14,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1991,4]]}},"alternative-id":["016792609190019H"],"URL":"https:\/\/doi.org\/10.1016\/0167-9260(91)90019-h","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1991,4]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"An analytic algorithm for global circuit placement","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-9260(91)90019-H","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1991 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}