{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T21:30:47Z","timestamp":1757626247434,"version":"3.44.0"},"reference-count":24,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1991,6,1]],"date-time":"1991-06-01T00:00:00Z","timestamp":675734400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1991,6,1]],"date-time":"1991-06-01T00:00:00Z","timestamp":675734400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1991,6]]},"DOI":"10.1016\/0167-9260(91)90048-p","type":"journal-article","created":{"date-parts":[[2003,3,14]],"date-time":"2003-03-14T14:37:33Z","timestamp":1047652653000},"page":"235-250","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":3,"title":["Formally verified synthesis of combinational CMOS circuits"],"prefix":"10.1016","volume":"11","author":[{"given":"David A.","family":"Basin","sequence":"first","affiliation":[]},{"given":"Geoffrey M.","family":"Brown","sequence":"additional","affiliation":[]},{"given":"Miriam E.","family":"Leeser","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"year":"1989","author":"Basin","article-title":"Implementing problem solving environments in constructive type theory","key":"10.1016\/0167-9260(91)90048-P_BIB1"},{"year":"1986","author":"Brayton","article-title":"Logic Minimization Algorithms for VLSI Synthesis","key":"10.1016\/0167-9260(91)90048-P_BIB2"},{"key":"10.1016\/0167-9260(91)90048-P_BIB3","series-title":"Proceedings of the 18th Des. Autom. Conf.","first-page":"786","article-title":"MOSSIM: a switch-level simulator for MOS LSI","author":"Bryant","year":"1981"},{"year":"1981","author":"Bryant","article-title":"A switch-level simulation model for integrated logic circuits","key":"10.1016\/0167-9260(91)90048-P_BIB4"},{"key":"10.1016\/0167-9260(91)90048-P_BIB5","doi-asserted-by":"crossref","first-page":"103","DOI":"10.1016\/0167-9260(87)90002-2","article-title":"Combinational static CMOS networks","volume":"5","author":"Brzozowski","year":"1987","journal-title":"INTEGRATION the VLSI j."},{"key":"10.1016\/0167-9260(91)90048-P_BIB6","series-title":"From HDL Descriptions to Guaranteed Correct Circuit Designs","article-title":"Hardware verification using higher-order logic","author":"Camillieri","year":"1986"},{"year":"1986","author":"Constable","article-title":"Implementing Mathematics with the Nuprl Proof Development System","key":"10.1016\/0167-9260(91)90048-P_BIB7"},{"key":"10.1016\/0167-9260(91)90048-P_BIB8","doi-asserted-by":"crossref","first-page":"537","DOI":"10.1147\/rd.285.0537","article-title":"LSS: A systemt for production logic synthesis","author":"Darringer","year":"1984","journal-title":"IBM J. Res. Develop."},{"issue":"4","key":"10.1016\/0167-9260(91)90048-P_BIB9","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/MDT.1985.294719","article-title":"A rule-based system for optimizing combinational logic","volume":"2","author":"De Geus","year":"1985","journal-title":"IEEE Des. Test Comput."},{"key":"10.1016\/0167-9260(91)90048-P_BIB10","first-page":"22","article-title":"Automating the layout of very large gate arrays","author":"Fujimara","year":"1988","journal-title":"VLSI Systems Design"},{"key":"10.1016\/0167-9260(91)90048-P_BIB11","first-page":"1140","article-title":"A unified switching theory with applications to VLSI design","volume":"70","author":"Hayes","year":"1982"},{"key":"10.1016\/0167-9260(91)90048-P_BIB12","article-title":"A calculus for the derivation of C-MOS switching circuits","author":"Hoare","year":"1988","journal-title":"Draft"},{"key":"10.1016\/0167-9260(91)90048-P_BIB13","series-title":"Sixth Int. Congr. Logic, Methodology and Philosophy of Science","first-page":"153","article-title":"Constructive mathematics and computer programming","author":"Martin-L\u00f6f","year":"1982"},{"key":"10.1016\/0167-9260(91)90048-P_BIB14","series-title":"Int. Work. Conf. The Fusion of Hardware Design and Verification","first-page":"26","article-title":"Using recursive types of reasoning about hardware in higher order logic","author":"Melham","year":"1988"},{"key":"10.1016\/0167-9260(91)90048-P_BIB15","first-page":"52","article-title":"Cell synthesis in action","author":"Meyer","year":"1988","journal-title":"VLSI Systems Design"},{"unstructured":"Moore, E.F., Table of four-relay contact networks, Bell Telephone Laboratories, Murray Hill NJ.","key":"10.1016\/0167-9260(91)90048-P_BIB16"},{"key":"10.1016\/0167-9260(91)90048-P_BIB17","doi-asserted-by":"crossref","first-page":"119","DOI":"10.1016\/0167-6423(83)90008-4","article-title":"A higher-order implementation of rewriting","volume":"3","author":"Paulson","year":"1983","journal-title":"Science of Computer Programming"},{"issue":"7","key":"10.1016\/0167-9260(91)90048-P_BIB18","doi-asserted-by":"crossref","first-page":"775","DOI":"10.1109\/43.3948","article-title":"Analysis and synthesis of combinational pass transistor networks","volume":"7","author":"Pedron","year":"1988","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"10.1016\/0167-9260(91)90048-P_BIB19","series-title":"Caltech Conference on VLSI","first-page":"399","article-title":"A notation for designing restoring logic circuitry in CMOS","author":"Rem","year":"1981"},{"key":"10.1016\/0167-9260(91)90048-P_BIB20","series-title":"Proc. 4th MIT Conf. Adv. Res. VLSI","first-page":"21","article-title":"ALPS: a generator of static CMOS layout from boolean expressions","author":"Serlet","year":"1986"},{"year":"1985","author":"Weste","series-title":"Principles of CMOS VLSI Design: A Systems Perspective","key":"10.1016\/0167-9260(91)90048-P_BIB21"},{"year":"1987","author":"Winskel","article-title":"A compositional model of MOS circuits","key":"10.1016\/0167-9260(91)90048-P_BIB22"},{"key":"10.1016\/0167-9260(91)90048-P_BIB23","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-18508-9_22","article-title":"Relating two models of hardware","author":"Winskel","year":"1987"},{"key":"10.1016\/0167-9260(91)90048-P_BIB24","series-title":"Proc. 24th Des. Autom. Conf.","first-page":"786","article-title":"A rule-based circuit representation for automated CMOS design and verification","author":"Wu","year":"1987"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016792609190048P?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016792609190048P?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T21:37:59Z","timestamp":1757453879000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016792609190048P"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,6]]},"references-count":24,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1991,6]]}},"alternative-id":["016792609190048P"],"URL":"https:\/\/doi.org\/10.1016\/0167-9260(91)90048-p","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1991,6]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Formally verified synthesis of combinational CMOS circuits","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-9260(91)90048-P","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1991 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}