{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T21:30:45Z","timestamp":1757626245117,"version":"3.44.0"},"reference-count":10,"publisher":"Elsevier BV","issue":"3","license":[{"start":{"date-parts":[[1991,6,1]],"date-time":"1991-06-01T00:00:00Z","timestamp":675734400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1991,6,1]],"date-time":"1991-06-01T00:00:00Z","timestamp":675734400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1991,6]]},"DOI":"10.1016\/0167-9260(91)90052-m","type":"journal-article","created":{"date-parts":[[2003,3,14]],"date-time":"2003-03-14T14:37:33Z","timestamp":1047652653000},"page":"317-327","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"title":["A logic minimization algorithm of functions with large DC-set"],"prefix":"10.1016","volume":"11","author":[{"given":"N.Q.","family":"Thang","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/0167-9260(91)90052-M_BIB1","series-title":"22nd Des. Autom. Conf.","first-page":"674","article-title":"Multiple output minimization","author":"Agrawal","year":"1985"},{"key":"10.1016\/0167-9260(91)90052-M_BIB2","unstructured":"Bertholomeus, M. and H. De Man, PRESTOL-II: Yet another logic minimizer for PLA, Proc. ISCAS 85 PP. 447\u2013454."},{"year":"1984","series-title":"Logic Minimization Algorithms for VLSI Synthesis","author":"Brayton","key":"10.1016\/0167-9260(91)90052-M_BIB3"},{"key":"10.1016\/0167-9260(91)90052-M_BIB4","series-title":"18th Des. Autom. Conf.","first-page":"301","article-title":"A state machine synthesizer \u2014 SMS","author":"Brown","year":"1981"},{"key":"10.1016\/0167-9260(91)90052-M_BIB5","doi-asserted-by":"crossref","first-page":"443","DOI":"10.1147\/rd.185.0443","article-title":"MINI: A heuritic approach for logic minimization","volume":"18","author":"Hong","year":"1974","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/0167-9260(91)90052-M_BIB6","series-title":"20th Des. Autom. Conf.","first-page":"545","article-title":"PRONTO: Quick PLA product reduction","author":"Martinez-Carballido","year":"1983"},{"article-title":"An optimal design method of PLAs","year":"1983","author":"Thang","key":"10.1016\/0167-9260(91)90052-M_BIB7"},{"key":"10.1016\/0167-9260(91)90052-M_BIB8","first-page":"64","article-title":"Transformation and minimization of a set of boolean equations","author":"Thang","year":"1987"},{"key":"10.1016\/0167-9260(91)90052-M_BIB9","series-title":"Eur. Conf. Circuit Theory and Design 1987","first-page":"339","article-title":"NEM_OP: Logic minimizer with output phase optimization for PLAs","author":"Thang","year":"1987"},{"key":"10.1016\/0167-9260(91)90052-M_BIB10","series-title":"22nd Des. Autom. Conf.","first-page":"739","article-title":"PHIPLA \u2014 A new algorithm for logic minimization","author":"Laarhoven","year":"1985"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016792609190052M?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:016792609190052M?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,9]],"date-time":"2025-09-09T21:37:57Z","timestamp":1757453877000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/016792609190052M"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,6]]},"references-count":10,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1991,6]]}},"alternative-id":["016792609190052M"],"URL":"https:\/\/doi.org\/10.1016\/0167-9260(91)90052-m","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1991,6]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A logic minimization algorithm of functions with large DC-set","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/0167-9260(91)90052-M","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1991 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}