{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,2,18]],"date-time":"2023-02-18T01:54:41Z","timestamp":1676685281513},"reference-count":13,"publisher":"Elsevier BV","issue":"13","license":[{"start":{"date-parts":[[1996,10,1]],"date-time":"1996-10-01T00:00:00Z","timestamp":844128000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computer Networks and ISDN Systems"],"published-print":{"date-parts":[[1996,10]]},"DOI":"10.1016\/0169-7552(95)00110-7","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T16:06:36Z","timestamp":1027613196000},"page":"1791-1807","source":"Crossref","is-referenced-by-count":4,"title":["The Helix switch: a single chip cell switch design"],"prefix":"10.1016","volume":"28","author":[{"given":"B.","family":"Patel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Schaffa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Willebeek-LeMair","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"2","key":"10.1016\/0169-7552(95)00110-7_BIB1","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/35.186359","article-title":"Architecture for ATM switching systems","volume":"31","author":"Zegura","year":"1993","journal-title":"IEEE Communication Magazine"},{"issue":"2","key":"10.1016\/0169-7552(95)00110-7_BIB2","doi-asserted-by":"crossref","first-page":"38","DOI":"10.1109\/35.186360","article-title":"Non-blocking architectures for atm switching","volume":"31","author":"Pattavina","year":"1993","journal-title":"IEEE Communication Magazine"},{"key":"10.1016\/0169-7552(95)00110-7_BIB3","article-title":"Survey of switching techniques in high-speed networks and their performance","volume":"Vol. 2","author":"Oie","year":"1990"},{"issue":"7","key":"10.1016\/0169-7552(95)00110-7_BIB4","doi-asserted-by":"crossref","DOI":"10.1109\/49.44557","article-title":"A survey of modern high-performance switching techniques","volume":"7","author":"Ahmadi","year":"1989","journal-title":"IEEE Journal on Selected Areas in Communications"},{"issue":"9","key":"10.1016\/0169-7552(95)00110-7_BIB5","doi-asserted-by":"crossref","DOI":"10.1109\/49.12886","article-title":"Queueing in high-performance packet switching","volume":"6","author":"Hluchyj","year":"1988","journal-title":"IEEE Journal on Selected Areas in Communications"},{"issue":"8","key":"10.1016\/0169-7552(95)00110-7_BIB6","article-title":"The Knockout switch: a simple, modular architecture for high performance packet switching","volume":"5","author":"Yeh","year":"1987","journal-title":"IEEE Journal on Selected Areas in Communications"},{"key":"10.1016\/0169-7552(95)00110-7_BIB7","series-title":"Proc. 1984 GLOBECOM","article-title":"Starlite: a wideband digital switch","author":"Huang","year":"1984"},{"key":"10.1016\/0169-7552(95)00110-7_BIB8","series-title":"Proc. 1991 IEEE INFOCOM","article-title":"SCOQ: a fast packet switch with shared concentration and output queueing","author":"Chen","year":"1991"},{"issue":"5","key":"10.1016\/0169-7552(95)00110-7_BIB9","doi-asserted-by":"crossref","first-page":"627","DOI":"10.1016\/0169-7552(94)00006-F","article-title":"Performance analysis of single-stage, output buffer packet switches with independent batch arrivals","volume":"27","author":"Bisdikian","year":"1995","journal-title":"Computer Networks and ISDN Systems"},{"key":"10.1016\/0169-7552(95)00110-7_BIB10","author":"Sauer","year":"1986"},{"issue":"1","key":"10.1016\/0169-7552(95)00110-7_BIB11","doi-asserted-by":"crossref","first-page":"35","DOI":"10.1109\/6.366233","article-title":"Technology 1995: solid state","volume":"32","author":"Geppert","year":"1995","journal-title":"IEEE Spectrum Magazine"},{"key":"10.1016\/0169-7552(95)00110-7_BIB12","author":"Weste","year":"1985"},{"key":"10.1016\/0169-7552(95)00110-7_BIB13","first-page":"165","article-title":"A logic design structure for LSI testability","volume":"Vol. 2","author":"Eichelberger","year":"1978"}],"container-title":["Computer Networks and ISDN Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0169755295001107?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:0169755295001107?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,26]],"date-time":"2019-04-26T11:27:45Z","timestamp":1556278065000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/0169755295001107"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,10]]},"references-count":13,"journal-issue":{"issue":"13","published-print":{"date-parts":[[1996,10]]}},"alternative-id":["0169755295001107"],"URL":"https:\/\/doi.org\/10.1016\/0169-7552(95)00110-7","relation":{},"ISSN":["0169-7552"],"issn-type":[{"value":"0169-7552","type":"print"}],"subject":[],"published":{"date-parts":[[1996,10]]}}}