{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T08:07:45Z","timestamp":1648886865400},"reference-count":8,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1996,9,1]],"date-time":"1996-09-01T00:00:00Z","timestamp":841536000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[1996,9]]},"DOI":"10.1016\/1383-7621(96)00016-1","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T22:26:53Z","timestamp":1027636013000},"page":"97-104","source":"Crossref","is-referenced-by-count":2,"title":["Experiences with VHDL and FPGAs"],"prefix":"10.1016","volume":"42","author":[{"given":"Lennart","family":"Lindh","sequence":"first","affiliation":[]},{"given":"Johan","family":"St\u00e4rner","sequence":"additional","affiliation":[]},{"given":"Joakim","family":"Adomat","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/1383-7621(96)00016-1_bib1","series-title":"93 \u00e5rs Konferens om Realtidssystem","article-title":"Survey of FASTHARD Real-Time Kernel Implemented in Special Hardware","author":"Lindh.","year":"1993"},{"key":"10.1016\/1383-7621(96)00016-1_bib2","series-title":"Real-Time Workshop","article-title":"FASTCHART A Fast Time Deterministic CPU and Hardware Based Real-Time-Kernel","author":"Lindh.","year":"1991"},{"key":"10.1016\/1383-7621(96)00016-1_bib3","unstructured":"[3] RTU Data Book. RF RealFast AB, Dragverksg 138, S-724 74 V\u00e4ster\u00e5s, Sweden"},{"key":"10.1016\/1383-7621(96)00016-1_bib4","series-title":"Proceedings of the International Conference on Computer Design","article-title":"The Spring Scheduling Co-processor: A Scheduling Accelerator","author":"Burleson.","year":"1993"},{"key":"10.1016\/1383-7621(96)00016-1_bib5","unstructured":"[5]Viewlogic Systems, Inc., 293 Boston Post Road West Marlboro, MA 01752-4615, USA"},{"key":"10.1016\/1383-7621(96)00016-1_bib6","unstructured":"[6]The VMEbus Specification ANSI\/IEEE STD1014-1987, IEC821 and 297. VMEbus International Trade Association, 10229 N. Scottsdale Road, Suite E, Scottsdale, AZ"},{"key":"10.1016\/1383-7621(96)00016-1_bib7","unstructured":"[7]XC4000 Data Book, XILINX. The Programmable Gate Array Company, 2100 Logic Drive, San Jose, CA 95124, USA"},{"key":"10.1016\/1383-7621(96)00016-1_bib8","unstructured":"[8]The Programmable Logic Data Book, XILINX. The Programmable Gate Array Company, 2100 Logic Drive, San Jose, CA 95124, USA"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:1383762196000161?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:1383762196000161?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,19]],"date-time":"2019-04-19T05:57:37Z","timestamp":1555653457000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/1383762196000161"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,9]]},"references-count":8,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1996,9]]}},"alternative-id":["1383762196000161"],"URL":"https:\/\/doi.org\/10.1016\/1383-7621(96)00016-1","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[1996,9]]}}}