{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T03:53:26Z","timestamp":1776916406294,"version":"3.51.2"},"reference-count":52,"publisher":"Elsevier","isbn-type":[{"value":"9780124202320","type":"print"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014]]},"DOI":"10.1016\/b978-0-12-420232-0.00001-5","type":"book-chapter","created":{"date-parts":[[2014,1,11]],"date-time":"2014-01-11T09:30:17Z","timestamp":1389432617000},"page":"1-66","source":"Crossref","is-referenced-by-count":2,"title":["Register-Level Communication in Speculative Chip Multiprocessors"],"prefix":"10.1016","author":[{"given":"Milan B.","family":"Radulovi\u0107","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Milo V.","family":"Toma\u0161evi\u0107","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Veljko M.","family":"Milutinovi\u0107","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0005","first-page":"500","article-title":"An architecture for mostly functional languages","author":"Knight","year":"1986"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0010","series-title":"Thread-Level Speculation, Encyclopedia of Parallel Computing","first-page":"1894","author":"Torrellas","year":"2011"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0015","first-page":"168","article-title":"Speculative chip multiprocessors","author":"Toma\u0161evi\u0107","year":"2005"},{"issue":"8","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0020","doi-asserted-by":"crossref","first-page":"1041","DOI":"10.1109\/TPDS.2007.1081","article-title":"CMP support for large and dependent speculative threads","volume":"18","author":"Colohan","year":"2007","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0025","first-page":"286","article-title":"Efficiency of thread-level speculation in SMT and CMP architectures\u2014Performance, power and thermal perspective","author":"Packirisamy","year":"2008"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0030","first-page":"474","article-title":"Boosting single-thread performance in multicore systems through fine-grain multithreading","author":"Madriles","year":"2009"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0035","series-title":"Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency","author":"Olukotun","year":"2007"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0040","series-title":"ICS-15","first-page":"368","article-title":"Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor","author":"Ooi","year":"2001"},{"issue":"9","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0045","doi-asserted-by":"crossref","first-page":"866","DOI":"10.1109\/12.795218","article-title":"A chip-multiprocessor architecture with speculative multithreading","volume":"48","author":"Krishnan","year":"1999","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0050","series-title":"Exploring Speculative Parallelism in SPEC2006","first-page":"77","author":"Packirisamy","year":"2009"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0055","first-page":"23","article-title":"Software thread-level speculation\u2014An optimistic library implementation","author":"Oancea","year":"2008"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0060","series-title":"Speculative N-Way Barriers","first-page":"1","author":"Ziarek","year":"2009"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0065","series-title":"Techniques to Reduce Thread-Level Speculation Overhead","author":"Warg","year":"2006"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0070","first-page":"414","article-title":"Multiscalar processors","author":"Sohi","year":"1995"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0075","first-page":"138","article-title":"Trace processors","author":"Rotenberg","year":"1997"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0080","first-page":"77","article-title":"Speculative multithreaded processors","author":"Marcuello","year":"1998"},{"issue":"6","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0085","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/40.888700","article-title":"The MAJC architecture: A synthesis of parallelism and scalability","volume":"20","author":"Tremblay","year":"2000","journal-title":"IEEE Micro"},{"issue":"4","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0090","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/MM.2000.865862","article-title":"A single-chip multiprocessor for smart terminals","volume":"20","author":"Edahiro","year":"2000","journal-title":"IEEE Micro"},{"issue":"7","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0095","doi-asserted-by":"crossref","first-page":"914","DOI":"10.1109\/TPDS.2007.70797","article-title":"Mitosis: A speculative multithreaded processor based on precomputation slices","volume":"19","author":"Madriles","year":"2008","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"issue":"3","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0100","doi-asserted-by":"crossref","first-page":"253","DOI":"10.1145\/1082469.1082471","article-title":"The STAMPede approach to thread-level speculation","volume":"23","author":"Gregory Steffan","year":"2005","journal-title":"ACM Trans. Comput. Syst."},{"issue":"1","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0105","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/TC.2005.12","article-title":"Scaling up the atlas chip-multiprocessor","volume":"54","author":"Sassone","year":"2005","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0110","first-page":"275","article-title":"A register communication mechanism for speculative multithreading chip multiprocessors","author":"Barli","year":"2003"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0115","first-page":"81","article-title":"Pinot: Speculative multi-threading processor architecture exploiting parallelism over a wide range of granularities","author":"Ohsawa","year":"2005"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0120","first-page":"1","article-title":"A scalable approach to thread-level speculation","author":"Steffan","year":"2000"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0125","series-title":"The Superthreaded Processor Architecture","first-page":"881","author":"Tsai","year":"1999"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0130","first-page":"306","article-title":"Exploiting fine-grain thread level parallelism on the MIT ALU processor","author":"Keckler","year":"1998"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0135","first-page":"85","article-title":"Hardware and software support for speculative execution of binaries on a chip-multiprocessor","author":"Krishnan","year":"1998"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0140","series-title":"Computer Organization and Design: The Hardware\/Software Interface","author":"Patterson","year":"2007"},{"issue":"4","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0145","doi-asserted-by":"crossref","first-page":"343","DOI":"10.1007\/s10766-006-0017-y","article-title":"Supporting microthread scheduling and synchronization in CMPs","volume":"34","author":"Bell","year":"2006","journal-title":"Int. J. Parallel Prog."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0150","first-page":"238","article-title":"Reducing register file size through instruction preexecution enhanced by value prediction","author":"Tanaka","year":"2009"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0155","doi-asserted-by":"crossref","first-page":"15","DOI":"10.5121\/ijesa.2012.2102","article-title":"Effect of thread-level parallelism on the performance of optimum architecture for embedded applications","volume":"2","author":"Alipour1","year":"2012","journal-title":"IJESA"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0160","first-page":"181","article-title":"The anatomy of the register file in a multiscalar processor","author":"Breach","year":"1994"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0165","first-page":"230","article-title":"Value prediction for speculative multithreaded architectures","author":"Marcuello","year":"1999"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0170","series-title":"Speculative Multithreaded Processors","author":"Marcuello","year":"2003"},{"issue":"1","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0175","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/12.902753","article-title":"Architecture of the atlas chip-multiprocessor: Dynamically parallelizing irregular applications","volume":"50","author":"Codrescu","year":"2001","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0180","series-title":"A hardware\/software approach for thread level control speculation","first-page":"67","author":"Hung","year":"2002"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0185","series-title":"Designing NEKO: A Speculative Multithreading Chip MultiProcessor","author":"Barli","year":"2004"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0190","article-title":"Executing sequential binaries on a multithreaded architecture with speculation support","author":"Krishnan","year":"1998"},{"issue":"1","key":"10.1016\/B978-0-12-420232-0.00001-5_bb0195","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1023\/A:1026479803767","article-title":"The need for fast communication in hardware-based speculative chip multiprocessors","volume":"29","author":"Krishnan","year":"2001","journal-title":"Int. J. Parallel Process."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0200","first-page":"1","article-title":"Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences","author":"Vajapeyam","year":"1997"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0205","first-page":"106","article-title":"Multiscalar execution along a single flow of control","author":"Sundararaman","year":"1997"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0210","first-page":"4","article-title":"Control independence in trace processors","author":"Rotenberg","year":"1999"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0215","first-page":"63","article-title":"Merlot: A single-chip tightly coupled four-way multi-thread processor","author":"Matsushita","year":"2000"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0220","unstructured":"MAJC Architecture Tutorial. Sun Microsystems, White Paper, 1999."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0225","first-page":"163","article-title":"MAJC-5200: A high performance microprocessor for multimedia computing","author":"Sudharsanan","year":"2000"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0230","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/2.546612","article-title":"Parallel programming with Polaris","volume":"29","author":"Blume","year":"1996","journal-title":"IEEE Comput."},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0235","first-page":"40","article-title":"On dynamic speculative thread partitioning and the MEM-slicing algorithm","author":"Codrescu","year":"1999"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0240","series-title":"The AMA correlated value predictor","author":"Codrescu","year":"1998"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0245","first-page":"405","article-title":"Towards an improved integrated coherence and speculation protocol","author":"Radulovi\u0107","year":"2007"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0250","series-title":"Cache Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions","author":"Toma\u0161evi\u0107","year":"1993"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0255","first-page":"88","article-title":"A proposal for register-level communication in a speculative chip multiprocessor","author":"Radulovi\u0107","year":"2005"},{"key":"10.1016\/B978-0-12-420232-0.00001-5_bb0260","first-page":"689","article-title":"An aggressive register-level communication in a speculative chip multiprocessor","author":"Radulovi\u0107","year":"2005"}],"container-title":["Advances in Computers"],"original-title":[],"language":"en","deposited":{"date-parts":[[2018,10,7]],"date-time":"2018-10-07T07:21:04Z","timestamp":1538896864000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/B9780124202320000015"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"ISBN":["9780124202320"],"references-count":52,"URL":"https:\/\/doi.org\/10.1016\/b978-0-12-420232-0.00001-5","relation":{},"ISSN":["0065-2458"],"issn-type":[{"value":"0065-2458","type":"print"}],"subject":[],"published":{"date-parts":[[2014]]}}}