{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T16:49:42Z","timestamp":1774716582519,"version":"3.50.1"},"reference-count":31,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Computers &amp; Electrical Engineering"],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1016\/j.compeleceng.2015.10.007","type":"journal-article","created":{"date-parts":[[2015,11,15]],"date-time":"2015-11-15T09:00:17Z","timestamp":1447578017000},"page":"225-234","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":34,"special_numbering":"C","title":["Hierarchical approach for hybrid wireless Network-on-chip in many-core era"],"prefix":"10.1016","volume":"51","author":[{"given":"Amin","family":"Rezaei","sequence":"first","affiliation":[]},{"given":"Masoud","family":"Daneshtalab","sequence":"additional","affiliation":[]},{"given":"Farshad","family":"Safaei","sequence":"additional","affiliation":[]},{"given":"Danella","family":"Zhao","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"1","key":"10.1016\/j.compeleceng.2015.10.007_bib0001","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","article-title":"Networks on chips: a new SoC paradigm","volume":"35","author":"Benini","year":"2002","journal-title":"IEEE Comput"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0002","series-title":"Proceedings of the IEEE international solid-state circuits conference (ISSCC)","first-page":"132","article-title":"How scaling will change processor architecture.","author":"Horowitz","year":"2004"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0003","series-title":"Routing algorithms in networks-on-chip","author":"Palesi","year":"2014"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0004","series-title":"Proceedings of the IEEE conference on industrial electronics and applications","first-page":"425","article-title":"A NoC performance evaluation platform supporting designs at multiple levels of abstraction","author":"Fu","year":"2009"},{"issue":"8","key":"10.1016\/j.compeleceng.2015.10.007_bib0005","doi-asserted-by":"crossref","first-page":"1025","DOI":"10.1109\/TC.2005.134","article-title":"Performance evaluation and design trade-offs for network-on-chip interconnect architectures","volume":"54","author":"Pande","year":"2005","journal-title":"IEEE Trans Comput"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0006","series-title":"Proceedings of computers and digital techniques","first-page":"261","article-title":"Network-on-chip architectures and design methods","author":"Benini","year":"2005"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0007","series-title":"Proceedings of international workshop on network on chip architectures (NoCArc)","first-page":"71","article-title":"Hybrid wireless network on chip: a new paradigm in multi-core design","author":"Pande","year":"2009"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0008","series-title":"Proceedings of IEEE international symposium on high performance computer architecture (HPCA)","first-page":"191","article-title":"CMP network-on-chip overlaid with multi-band RF-interconnect","author":"Chang","year":"2008"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0009","series-title":"Proceedings of IEEE international high performance computing & simulation (HPCS)","first-page":"499","article-title":"HiWA: a hierarchical wireless network-on-chip architecture","author":"Rezaei","year":"2014"},{"issue":"10","key":"10.1016\/j.compeleceng.2015.10.007_bib0010","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","article-title":"3-D topologies for networks-on-chip","volume":"15","author":"Pavlidis","year":"2007","journal-title":"IEEE Trans Very Large Scale Integr"},{"issue":"9","key":"10.1016\/j.compeleceng.2015.10.007_bib0011","doi-asserted-by":"crossref","first-page":"1246","DOI":"10.1109\/TC.2008.78","article-title":"Photonic networks-on-chip for future generations of chip multiprocessors","volume":"57","author":"Shacham","year":"2008","journal-title":"IEEE Trans Comput"},{"issue":"2","key":"10.1016\/j.compeleceng.2015.10.007_bib0012","doi-asserted-by":"crossref","first-page":"186","DOI":"10.1109\/TCAD.2014.2379640","article-title":"A new frontier in ultralow power wireless links: network-on-chip and chip-to-chip interconnects","volume":"34","author":"Laha","year":"2015","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0013","first-page":"324","article-title":"Cost-optimal design of wireless pre-bonding test framework","author":"Chandran","year":"2014","journal-title":"IEEE Int Syst Chip Conf (SOCC)"},{"issue":"12","key":"10.1016\/j.compeleceng.2015.10.007_bib0014","doi-asserted-by":"crossref","first-page":"2730","DOI":"10.1109\/JSSC.2008.2004868","article-title":"Terahertz CMOS frequency generator using linear superposition technique","volume":"43","author":"Huang","year":"2008","journal-title":"IEEE J Solid-State Circ"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0015","first-page":"472","article-title":"A 410GHz CMOS push-push oscillator with an on-chip patch antenna","author":"Seok","year":"2008","journal-title":"IEEE Int Solid-State Circ Conf (ISSCC)"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0016","series-title":"Proceedings of the international conference on mobile computing and networking (MobiCom)","first-page":"217","article-title":"A scalable micro wireless interconnect structure for CMPs","author":"Lee","year":"2009"},{"issue":"25","key":"10.1016\/j.compeleceng.2015.10.007_bib0017","doi-asserted-by":"crossref","first-page":"17106","DOI":"10.1364\/OE.15.017106","article-title":"Ultra-compact, low RF power, 10 Gb\/s silicon Mach-Zehnder modulato","volume":"15","author":"Green","year":"2007","journal-title":"Opt Express"},{"issue":"9","key":"10.1016\/j.compeleceng.2015.10.007_bib0018","doi-asserted-by":"crossref","first-page":"1230","DOI":"10.1109\/TC.2008.86","article-title":"SD-MAC: design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip","volume":"57","author":"Zhao","year":"2008","journal-title":"IEEE Trans Comput"},{"issue":"2","key":"10.1016\/j.compeleceng.2015.10.007_bib0019","doi-asserted-by":"crossref","first-page":"228","DOI":"10.1109\/JETCAS.2012.2193835","article-title":"Wireless NoC as interconnection backbone for multicore chips: promises and challenges","volume":"2","author":"Deb","year":"2012","journal-title":"IEEE J Emerg Select Top Circ Syst"},{"issue":"11","key":"10.1016\/j.compeleceng.2015.10.007_bib0020","doi-asserted-by":"crossref","first-page":"137","DOI":"10.1109\/MCOM.2013.6658665","article-title":"Graphene-enabled wireless communication for massive multicore architectures","volume":"51","author":"Abadal","year":"2013","journal-title":"IEEE Commun Mag"},{"issue":"10","key":"10.1016\/j.compeleceng.2015.10.007_bib0021","doi-asserted-by":"crossref","first-page":"1485","DOI":"10.1109\/TC.2010.176","article-title":"Scalable hybrid wireless network-on-chip architectures for multicore systems","volume":"60","author":"Ganguly","year":"2011","journal-title":"IEEE Trans Comput"},{"issue":"8","key":"10.1016\/j.compeleceng.2015.10.007_bib0022","doi-asserted-by":"crossref","first-page":"1678","DOI":"10.1109\/JSSC.2007.900236","article-title":"Communication using antennas fabricated in silicon integrated circuits","volume":"42","author":"Lin;","year":"2007","journal-title":"IEEE J Solid-State Circ"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0023","series-title":"Ant colony optimization","author":"Dorigo","year":"2004"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0024","series-title":"Adapting the pheromone evaporation rate in dynamic routing problems","author":"Mavrovouniotis","year":"2013"},{"issue":"2-3","key":"10.1016\/j.compeleceng.2015.10.007_bib0025","doi-asserted-by":"crossref","first-page":"243","DOI":"10.1016\/j.tcs.2005.05.020","article-title":"Ant colony optimization theory: a survey","volume":"344","author":"Dorigo","year":"2005","journal-title":"Elsevier J Theor Comput Sci"},{"issue":"4","key":"10.1016\/j.compeleceng.2015.10.007_bib0026","doi-asserted-by":"crossref","first-page":"910","DOI":"10.1109\/TSMCB.2009.2012867","article-title":"A pheromone-rate-based analysis on the convergence time of ACO algorithm","volume":"39","author":"Huang","year":"2009","journal-title":"IEEE Trans Syst, Man, Cybern, Part B: Cybern"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0027","series-title":"Proceedings of IEEE euromicro conference on parallel, distributed and network-based computing (PDP)","first-page":"421","article-title":"Dynamic application mapping algorithm for wireless network-on-chip","author":"Rezaei","year":"2015"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0028","doi-asserted-by":"crossref","unstructured":"Nayebi A, Meraji S, Shamaei A, and Sarbazi-Azad H. \u201cXMulator: A listener-based integrated simulation platform for interconnection networks,\u201d In Asia International Conference on Modeling & Simulation (AMS), pp. 128-132, 2007.","DOI":"10.1109\/AMS.2007.112"},{"issue":"1","key":"10.1016\/j.compeleceng.2015.10.007_bib0029","doi-asserted-by":"crossref","first-page":"191","DOI":"10.1109\/TVLSI.2010.2091686","article-title":"Orion 2.0: A power-area simulator for interconnection networks","volume":"20","author":"Kahng","year":"2012","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0030","doi-asserted-by":"crossref","unstructured":"Woo S.C., Ohara M, Torrie E, Singh J.P., and Gupta A. \u201cThe SPLASH-2 programs: characterization and methodological considerations,\u201d In International Symposium on Computer Architecture (ISCA), pp. 24-36, 1995.","DOI":"10.1145\/223982.223990"},{"key":"10.1016\/j.compeleceng.2015.10.007_bib0031","unstructured":"ITRS. International Technology Roadmap for Semiconductors, 2007 edition."}],"container-title":["Computers &amp; Electrical Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0045790615003523?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0045790615003523?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2018,9,17]],"date-time":"2018-09-17T13:56:08Z","timestamp":1537192568000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0045790615003523"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":31,"alternative-id":["S0045790615003523"],"URL":"https:\/\/doi.org\/10.1016\/j.compeleceng.2015.10.007","relation":{},"ISSN":["0045-7906"],"issn-type":[{"value":"0045-7906","type":"print"}],"subject":[],"published":{"date-parts":[[2016,4]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Hierarchical approach for hybrid wireless Network-on-chip in many-core era","name":"articletitle","label":"Article Title"},{"value":"Computers & Electrical Engineering","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.compeleceng.2015.10.007","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2015 Elsevier Ltd. All rights reserved.","name":"copyright","label":"Copyright"}]}}